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Revision to expose option in setundef pass 

Corrects indentation

Simplifications and corrections
This commit is contained in:
Aman Goel 2018-08-18 09:08:07 +05:30
parent 61f002c908
commit 83b41260f6
1 changed files with 108 additions and 139 deletions
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79
passes/cmds/setundef.cc
View File

@ -33,31 +33,16 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
{
RTLIL::Wire *wire = NULL;
name = RTLIL::escape_id(name);
if (module->count_id(name) != 0)
{
if (module->wires_.count(name) > 0)
wire = module->wires_.at(name);
if (wire != NULL && wire->width != width)
wire = NULL;
if (wire != NULL && wire->port_input != flag_input)
wire = NULL;
if (wire != NULL && wire->port_output != flag_output)
wire = NULL;
if (wire == NULL) {
return wire;
log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str());
}
log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
name += "$";
return add_wire(module, name, width, flag_input, flag_output);
}
else
{
@ -73,26 +58,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std:
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
}
if (!flag_global)
return wire;
for (auto &it : module->cells_)
{
if (design->modules_.count(it.second->type) == 0)
continue;
RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->hasPort(name))
continue;
it.second->setPort(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
}
return wire;
}
@ -262,7 +227,8 @@ struct SetundefPass : public Pass {
if (!module->processes.empty())
log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
if (expose_mode) {
if (expose_mode)
{
SigMap sigmap(module);
dict<SigBit, bool> wire_drivers;
pool<SigBit> used_wires;
@ -273,15 +239,13 @@ struct SetundefPass : public Pass {
SigSpec sig = sigmap(conn.second);
if (cell->input(conn.first))
for (auto bit : sig)
if (bit.wire) {
if (bit.wire)
used_wires.insert(bit);
}
if (cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++) {
for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire)
wire_drivers[sig[i]] = true;
}
}
for (auto wire : module->wires()) {
if (wire->port_input) {
@ -289,17 +253,18 @@ struct SetundefPass : public Pass {
for (int i = 0; i < GetSize(sig); i++)
wire_drivers[sig[i]] = true;
}
if (wire->port_output)
for (auto bit : sigmap(wire))
if (bit.wire) used_wires.insert(bit);
if (wire->port_output) {
SigSpec sig = sigmap(wire);
for (auto bit : sig)
if (bit.wire)
used_wires.insert(bit);
}
}
pool<RTLIL::Wire*> undriven_wires;
for (auto bit : used_wires) {
if (!wire_drivers.count(bit)) {
for (auto bit : used_wires)
if (!wire_drivers.count(bit))
undriven_wires.insert(bit.wire);
}
}
for (auto &it : undriven_wires)
undriven_signals.add(sigmap(it));
@ -320,18 +285,17 @@ struct SetundefPass : public Pass {
if (c.wire->width == c.width) {
wire = c.wire;
wire->port_input = true;
}
else {
} else {
string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
wire = add_wire(design, module, name, c.width, true, false, false);
wire = add_wire(module, name, c.width, true, false);
module->connect(RTLIL::SigSig(c, wire));
}
log("Exposing undriven wire %s as input.\n", wire->name.c_str());
}
module->fixup_ports();
continue;
}
else {
else
{
SigMap sigmap(module);
SigPool undriven_signals;
@ -351,6 +315,11 @@ struct SetundefPass : public Pass {
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ)
bits = module->Anyseq(NEW_ID, c.width);
else if (worker.next_bit_mode == MODE_ANYCONST)
bits = module->Anyconst(NEW_ID, c.width);
else
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
module->connect(RTLIL::SigSig(c, bits));