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anlogic : Fix alu mapping

This commit is contained in:
Miodrag Milanovic 2019-08-03 14:47:33 +02:00
parent 44a9dcbbbf
commit 837cb0a1b9
1 changed files with 8 additions and 16 deletions
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24
techlibs/anlogic/arith_map.v
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@ -42,10 +42,9 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI}; wire [Y_WIDTH+2:0] C = {COx, CI};
wire dummy; wire dummy;
(* keep *)
AL_MAP_ADDER #( AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY")) .ALUTYPE("ADD_CARRY"))
adder_cin ( adder_cin (
@ -55,19 +54,6 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *)
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.c(C[Y_WIDTH]),
.o(COx[Y_WIDTH])
);
assign CO = COx[Y_WIDTH];
end
else
begin
(* keep *)
AL_MAP_ADDER #( AL_MAP_ADDER #(
.ALUTYPE("ADD") .ALUTYPE("ADD")
) adder_i ( ) adder_i (
@ -76,9 +62,15 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
.c(C[i+1]), .c(C[i+1]),
.o({COx[i+1],Y[i]}) .o({COx[i+1],Y[i]})
); );
end
end: slice end: slice
endgenerate endgenerate
/* End implementation */ /* End implementation */
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.c(C[Y_WIDTH+1]),
.o(COx[Y_WIDTH+1])
);
assign CO = COx[Y_WIDTH+1];
assign X = AA ^ BB; assign X = AA ^ BB;
endmodule endmodule