riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

read_aiger: add -xaiger option

This commit is contained in:
Eddie Hung 2020-01-06 12:43:29 -08:00
parent b70e87137d
commit 83616e7866
1 changed files with 17 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
frontends/aiger/aigerparse.cc
View File

@ -1000,18 +1000,21 @@ struct AigerFrontend : public Frontend {
log("Load module from an AIGER file into the current design.\n"); log("Load module from an AIGER file into the current design.\n");
log("\n"); log("\n");
log(" -module_name <module_name>\n"); log(" -module_name <module_name>\n");
log(" Name of module to be created (default: <filename>)\n"); log(" name of module to be created (default: <filename>)\n");
log("\n"); log("\n");
log(" -clk_name <wire_name>\n"); log(" -clk_name <wire_name>\n");
log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n"); log(" if specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n"); log(" clocked by wire of this name. otherwise, $_FF_ cells will be used\n");
log("\n"); log("\n");
log(" -map <filename>\n"); log(" -map <filename>\n");
log(" read file with port and latch symbols\n"); log(" read file with port and latch symbols\n");
log("\n"); log("\n");
log(" -wideports\n"); log(" -wideports\n");
log(" Merge ports that match the pattern 'name[int]' into a single\n"); log(" merge ports that match the pattern 'name[int]' into a single\n");
log(" multi-bit port 'name'.\n"); log(" multi-bit port 'name'\n");
log("\n");
log(" -xaiger\n");
log(" read XAIGER extensions\n");
log("\n"); log("\n");
} }
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -1021,7 +1024,7 @@ struct AigerFrontend : public Frontend {
RTLIL::IdString clk_name = "\\clk"; RTLIL::IdString clk_name = "\\clk";
RTLIL::IdString module_name; RTLIL::IdString module_name;
std::string map_filename; std::string map_filename;
bool wideports = false; bool wideports = false, xaiger = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
@ -1042,6 +1045,10 @@ struct AigerFrontend : public Frontend {
wideports = true; wideports = true;
continue; continue;
} }
if (arg == "-xaiger") {
xaiger = true;
continue;
}
break; break;
} }
extra_args(f, filename, args, argidx, true); extra_args(f, filename, args, argidx, true);
@ -1061,7 +1068,10 @@ struct AigerFrontend : public Frontend {
} }
AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports); AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
reader.parse_aiger(); if (xaiger)
reader.parse_xaiger();
else
reader.parse_aiger();
} }
} AigerFrontend; } AigerFrontend;