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Fix signed multiplier decomposition

This commit is contained in:
Eddie Hung 2019-07-18 13:11:26 -07:00
parent 5562cb08a4
commit 8326af5418
1 changed files with 36 additions and 29 deletions
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43
techlibs/common/mul2dsp.v
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@ -5,14 +5,11 @@
`ifndef DSP_A_MAXWIDTH `ifndef DSP_A_MAXWIDTH
$error("Macro DSP_A_MAXWIDTH must be defined"); $error("Macro DSP_A_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_A_SIGNEDONLY
`define DSP_A_SIGNEDONLY 0
`endif
`ifndef DSP_B_MAXWIDTH `ifndef DSP_B_MAXWIDTH
$error("Macro DSP_B_MAXWIDTH must be defined"); $error("Macro DSP_B_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_B_SIGNEDONLY `ifndef DSP_SIGNEDONLY
`define DSP_B_SIGNEDONLY 0 `define DSP_SIGNEDONLY 0
`endif `endif
`ifndef DSP_NAME `ifndef DSP_NAME
@ -34,7 +31,9 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
if (`DSP_SIGNEDONLY && !A_SIGNED) begin if (A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1;
else if (`DSP_SIGNEDONLY && !A_SIGNED) begin
wire [1:0] dummy; wire [1:0] dummy;
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
@ -100,12 +99,18 @@ module \$__mul_gen (A, B, Y);
if (A_WIDTH > `DSP_A_MAXWIDTH) begin if (A_WIDTH > `DSP_A_MAXWIDTH) begin
localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
wire [partial_Y_WIDTH-1:0] partial [n-1:1]; if (A_SIGNED && B_SIGNED) begin
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
end
else begin
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
wire [Y_WIDTH-1:0] partial_sum [n-1:0]; wire [Y_WIDTH-1:0] partial_sum [n-1:0];
end
\$__mul_gen #( \$__mul_gen #(
.A_SIGNED(0), .A_SIGNED(0),
.B_SIGNED(0), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
@ -119,7 +124,7 @@ module \$__mul_gen (A, B, Y);
for (i = 1; i < n-1; i=i+1) begin:slice for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul_gen #( \$__mul_gen #(
.A_SIGNED(0), .A_SIGNED(0),
.B_SIGNED(0), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
@ -136,24 +141,26 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH), .Y_WIDTH(partial_Y_WIDTH)
) mul_slice_last ( ) mul_slice_last (
.A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
.B(B), .B(B),
.Y(partial[n-1]) .Y(partial[n-1])
); );
assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
assign Y = partial_sum[n-1];
end end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
`ifdef DSP_B_SIGNEDONLY
localparam sign_headroom = 1;
`else
localparam sign_headroom = 0;
`endif
localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);
wire [partial_Y_WIDTH-1:0] partial [n-1:1]; if (A_SIGNED && B_SIGNED) begin
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
end
else begin
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
wire [Y_WIDTH-1:0] partial_sum [n-1:0]; wire [Y_WIDTH-1:0] partial_sum [n-1:0];
end
\$__mul_gen #( \$__mul_gen #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
@ -188,7 +195,7 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)),
.Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) .Y_WIDTH(partial_Y_WIDTH)
) mul_last ( ) mul_last (
.A(A), .A(A),
.B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),