mirror of https://github.com/YosysHQ/yosys.git
write_verilog: Handle edge case with non-pruned processes
This change only matters for processes that weren't processed by `proc_rmdead` for which follow-up cases after a default case are treated differently in Verilog and RTLIL semantics.
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@ -1988,12 +1988,10 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
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dump_sigspec(f, sw->signal);
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dump_sigspec(f, sw->signal);
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f << stringf(")\n");
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f << stringf(")\n");
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bool got_default = false;
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
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bool got_default = false;
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dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true);
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dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true);
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if ((*it)->compare.size() == 0) {
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if ((*it)->compare.size() == 0) {
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if (got_default)
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continue;
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f << stringf("%s default", indent.c_str());
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f << stringf("%s default", indent.c_str());
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got_default = true;
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got_default = true;
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} else {
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} else {
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@ -2006,6 +2004,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
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}
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}
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f << stringf(":\n");
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f << stringf(":\n");
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dump_case_body(f, indent + " ", *it);
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dump_case_body(f, indent + " ", *it);
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if (got_default) {
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// If we followed up the default with more cases the Verilog
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// semantics would be to match those *before* the default, but
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// the RTLIL semantics are to match those *after* the default
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// (so they can never be selected). Exit now.
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break;
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}
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}
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}
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if (sw->cases.empty()) {
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if (sw->cases.empty()) {
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