start splitting blackboxes and add wrapper techmap

techlibs/nanoxplore/Makefile.inc

@@ -4,7 +4,13 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o
 # Techmap
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))

techlibs/nanoxplore/cells_bb.v

@@ -419,21 +419,6 @@ module NX_CKS(CKI, CMD, CKO);
     parameter ck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_CKS_U(CKI, CMD, CKO);
-    input CKI;
-    output CKO;
-    input CMD;
-endmodule
-
-(* blackbox *)
-module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
-    input CKI0;
-    input CKI1;
-    output CKO;
-    input SEL;
-endmodule
-
 (* blackbox *)
 module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
@@ -2839,17 +2824,6 @@ module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11
     parameter wck_edge = 1'b0;
 endmodule
 
-(* blackbox *)
-module NX_GCK_U(SI1, SI2, CMD, SO);
-    input CMD;
-    input SI1;
-    input SI2;
-    output SO;
-    parameter inv_in = 1'b0;
-    parameter inv_out = 1'b0;
-    parameter std_mode = "BYPASS";
-endmodule
-
 (* blackbox *)
 module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
 , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o

techlibs/nanoxplore/cells_bb_u.v

@@ -0,0 +1,10 @@
+(* blackbox *)
+module NX_GCK_U(SI1, SI2, CMD, SO);
+    input CMD;
+    input SI1;
+    input SI2;
+    output SO;
+    parameter inv_in = 1'b0;
+    parameter inv_out = 1'b0;
+    parameter std_mode = "BYPASS";
+endmodule

techlibs/nanoxplore/cells_wrap_u.v

@@ -0,0 +1,34 @@
+module NX_CKS_U(CKI, CMD, CKO);
+    input CKI;
+    output CKO;
+    input CMD;
+
+NX_GCK_U #(
+    .inv_in(1'b0),
+    .inv_out(1'b0),
+    .std_mode("CKS")
+) _TECHMAP_REPLACE_ (
+    .CMD(CMD),
+    .SI1(CKI),
+    .SI2(1'b0),
+    .SO(CKO)
+);
+endmodule
+
+module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
+    input CKI0;
+    input CKI1;
+    output CKO;
+    input SEL;
+
+NX_GCK_U #(
+    .inv_in(1'b0),
+    .inv_out(1'b0),
+    .std_mode("MUX")
+) _TECHMAP_REPLACE_ (
+    .CMD(SEL),
+    .SI1(CKI0),
+    .SI2(CKI1),
+    .SO(CKO)
+);
+endmodule

techlibs/nanoxplore/synth_nanoxplore.cc

@@ -93,6 +93,7 @@ struct SynthNanoXplorePass : public ScriptPass
 
 	string top_opt, json_file, family;
 	bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad;
+	std::string postfix;
 
 	void clear_flags() override
 	{
@@ -106,6 +107,7 @@ struct SynthNanoXplorePass : public ScriptPass
 		nobram = false;
 		nodsp = false;
 		iopad = false;
+		postfix = "";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -175,8 +177,20 @@ struct SynthNanoXplorePass : public ScriptPass
 		if (family.empty()) {
 			//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
 			family = "ultra";
+			postfix = "_u";
 		}
 
+		if (family == "ultra") {
+			postfix = "_u";
+		} else if (family == "u300") {
+			postfix = "_u";
+		} else if (family == "medium") {
+			postfix = "_m";
+		} else if (family == "large") {
+			postfix = "_l";
+		} else 
+			log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
@@ -192,7 +206,8 @@ struct SynthNanoXplorePass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v");
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}