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Merge pull request #1330 from YosysHQ/clifford/fix1145 

Add flatten handling of pre-existing wires as created by interfaces
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Clifford Wolf 2019-09-05 18:10:40 +02:00 committed by GitHub
parent 8d91960663 71d355560e
commit 82784c279d
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2 changed files with 40 additions and 8 deletions
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4
README.md
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@ -332,6 +332,10 @@ Verilog Attributes and non-standard features
that represent module parameters or localparams (when the HDL front-end that represent module parameters or localparams (when the HDL front-end
is run in ``-pwires`` mode). is run in ``-pwires`` mode).
- Wires marked with the ``hierconn`` attribute are connected to wires with the
same name (format ``cell_name.identifier``) when they are imported from
sub-modules by ``flatten``.
- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
from inserting another clock buffer on a net driven by such output. from inserting another clock buffer on a net driven by such output.

44
passes/techmap/techmap.cc
View File

@ -205,20 +205,38 @@ struct TechmapWorker
} }
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports; std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
dict<Wire*, IdString> temp_renamed_wires;
for (auto &it : tpl->wires_) { for (auto &it : tpl->wires_) {
if (it.second->port_id > 0) if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first; positional_ports[stringf("$%d", it.second->port_id)] = it.first;
IdString w_name = it.second->name; IdString w_name = it.second->name;
apply_prefix(cell->name, w_name); apply_prefix(cell->name, w_name);
RTLIL::Wire *w = module->addWire(w_name, it.second); RTLIL::Wire *w = module->wire(w_name);
w->port_input = false; if (w != nullptr) {
w->port_output = false; if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
w->port_id = 0; temp_renamed_wires[w] = w->name;
if (it.second->get_bool_attribute(ID(_techmap_special_))) module->rename(w, NEW_ID);
w->attributes.clear(); w = nullptr;
if (w->attributes.count(ID(src))) } else {
w->add_strpool_attribute(ID(src), extra_src_attrs); w->attributes.erase(ID(hierconn));
if (GetSize(w) < GetSize(it.second)) {
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
w->width = GetSize(it.second);
}
}
}
if (w == nullptr) {
w = module->addWire(w_name, it.second);
w->port_input = false;
w->port_output = false;
w->port_id = 0;
if (it.second->get_bool_attribute(ID(_techmap_special_)))
w->attributes.clear();
if (w->attributes.count(ID(src)))
w->add_strpool_attribute(ID(src), extra_src_attrs);
}
design->select(module, w); design->select(module, w);
} }
@ -380,6 +398,16 @@ struct TechmapWorker
} }
module->remove(cell); module->remove(cell);
for (auto &it : temp_renamed_wires)
{
Wire *w = it.first;
IdString name = it.second;
IdString altname = module->uniquify(name);
Wire *other_w = module->wire(name);
module->rename(other_w, altname);
module->rename(w, name);
}
} }
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,