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ALU sim tweaks

This commit is contained in:
Pepijn de Vos 2019-10-24 13:39:43 +02:00
parent 83fbfe0964
commit 8226f2db0b
2 changed files with 13 additions and 13 deletions
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22
techlibs/gowin/cells_sim.v
View File

@ -280,16 +280,16 @@ input CIN;
output SUM; output SUM;
output COUT; output COUT;
parameter ADD = 0; localparam ADD = 0;
parameter SUB = 1; localparam SUB = 1;
parameter ADDSUB = 2; localparam ADDSUB = 2;
parameter NE = 3; localparam NE = 3;
parameter GE = 4; localparam GE = 4;
parameter LE = 5; localparam LE = 5;
parameter CUP = 6; localparam CUP = 6;
parameter CDN = 7; localparam CDN = 7;
parameter CUPCDN = 8; localparam CUPCDN = 8;
parameter MULT = 9; localparam MULT = 9;
parameter ALU_MODE = 0; parameter ALU_MODE = 0;
@ -298,7 +298,7 @@ reg S, C;
assign SUM = S ^ CIN; assign SUM = S ^ CIN;
assign COUT = S? CIN : C; assign COUT = S? CIN : C;
always @(I0, I1, I3,CIN) begin always @* begin
case (ALU_MODE) case (ALU_MODE)
ADD: begin ADD: begin
S = I0 ^ I1; S = I0 ^ I1;

4
tests/arch/gowin/mux.ys
View File

@ -42,8 +42,8 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4 select -assert-count 10 t:LUT4
select -assert-count 3 t:LUT3 select -assert-count 1 t:LUT3
select -assert-count 20 t:IBUF select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF select -assert-count 1 t:OBUF