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Merge pull request #1204 from smunaut/fix_1187 

ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
This commit is contained in:
David Shah 2019-07-17 07:55:26 +01:00 committed by GitHub
parent f8e470c1d1 f28e38de99
commit 82153059a1
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 4 additions and 4 deletions
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6
techlibs/ice40/ice40_unlut.cc
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@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
cell->unsetParam("\\LUT_INIT"); cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({ cell->setPort("\\A", SigSpec({
get_bit_or_zero(cell->getPort("\\I3")), get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")), get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0")) get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I3"))
})); }));
cell->setPort("\\Y", cell->getPort("\\O")[0]); cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->unsetPort("\\I0"); cell->unsetPort("\\I0");

2
techlibs/ice40/synth_ice40.cc
View File

@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
} }
run("clean"); run("clean");
run("ice40_unlut"); run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
} }
if (check_label("map_cells")) if (check_label("map_cells"))