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Use left-recursive rule for cell_port_list in Verilog parser.

This commit is contained in:
Andrew Becker 2016-03-14 19:28:34 +01:00 committed by Clifford Wolf
parent 2a8d5e64f5
commit 81d4e9e7c1
1 changed files with 10 additions and 6 deletions
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16
frontends/verilog/verilog_parser.y
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@ -801,14 +801,14 @@ single_cell:
astbuf2->str = *$1; astbuf2->str = *$1;
delete $1; delete $1;
ast_stack.back()->children.push_back(astbuf2); ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')' | } '(' cell_port_list_opt ')' |
TOK_ID non_opt_range { TOK_ID non_opt_range {
astbuf2 = astbuf1->clone(); astbuf2 = astbuf1->clone();
if (astbuf2->type != AST_PRIMITIVE) if (astbuf2->type != AST_PRIMITIVE)
astbuf2->str = *$1; astbuf2->str = *$1;
delete $1; delete $1;
ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
} '(' cell_port_list ')'; } '(' cell_port_list_opt ')';
prim_list: prim_list:
single_prim | single_prim |
@ -819,7 +819,7 @@ single_prim:
/* no name */ { /* no name */ {
astbuf2 = astbuf1->clone(); astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2); ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')'; } '(' cell_port_list_opt ')';
cell_parameter_list_opt: cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */; '#' '(' cell_parameter_list ')' | /* empty */;
@ -842,14 +842,18 @@ cell_parameter:
delete $2; delete $2;
}; };
cell_port_list: cell_port_list_opt:
/* empty */ | cell_port | /* empty */ |
cell_port ',' cell_port_list | cell_port_list |
/* empty */ ',' { /* empty */ ',' {
AstNode *node = new AstNode(AST_ARGUMENT); AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node); astbuf2->children.push_back(node);
} cell_port_list; } cell_port_list;
cell_port_list:
cell_port |
cell_port_list ',' cell_port;
cell_port: cell_port:
expr { expr {
AstNode *node = new AstNode(AST_ARGUMENT); AstNode *node = new AstNode(AST_ARGUMENT);