riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Removed debug log from const_pow()

This commit is contained in:
Clifford Wolf 2013-11-08 04:43:38 +01:00
parent fc6dc0d7b8
commit 81b8f3292e
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
kernel/calc.cc
View File

@ -454,7 +454,6 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
{ {
int undef_bit_pos = -1; int undef_bit_pos = -1;
log("--POW--\n");
BigInteger a = const2big(arg1, signed1, undef_bit_pos); BigInteger a = const2big(arg1, signed1, undef_bit_pos);
BigInteger b = const2big(arg2, signed2, undef_bit_pos); BigInteger b = const2big(arg2, signed2, undef_bit_pos);
BigInteger y = 1; BigInteger y = 1;