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Remove EXPLICIT_CARRY logic. 

The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-08-19 08:42:09 -07:00 committed by Marcelina Kościelnicka
parent 57af8499df
commit 819f1d8c20
3 changed files with 2 additions and 150 deletions
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114
techlibs/xilinx/arith_map.v
View File

@ -35,13 +35,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
genvar i; genvar i;
`ifdef _EXPLICIT_CARRY generate if (`LUT_SIZE == 4) begin
localparam EXPLICIT_CARRY = 1'b1;
`else
localparam EXPLICIT_CARRY = 1'b0;
`endif
generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
(* force_downto *) (* force_downto *)
wire [WIDTH-1:0] C = {CO, CI}; wire [WIDTH-1:0] C = {CO, CI};
@ -135,12 +129,6 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
`ifdef _EXPLICIT_CARRY
localparam EXPLICIT_CARRY = 1'b1;
`else
localparam EXPLICIT_CARRY = 1'b0;
`endif
generate if (`LUT_SIZE == 4) begin generate if (`LUT_SIZE == 4) begin
(* force_downto *) (* force_downto *)
@ -163,106 +151,6 @@ generate if (`LUT_SIZE == 4) begin
); );
end endgenerate end endgenerate
end else if (EXPLICIT_CARRY) begin
(* force_downto *)
wire [Y_WIDTH-1:0] S = AA ^ BB;
wire CINIT;
// Carry chain.
//
// VPR requires that the carry chain never hit the fabric. The CO input
// to this techmap is the carry outputs for synthesis, e.g. might hit the
// fabric.
//
// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
// e.g. off fabric dedicated chain. CO is the carry outputs that are
// available to the fabric.
(* force_downto *)
wire [Y_WIDTH-1:0] CO_CHAIN;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
// If carry chain is being initialized to a constant, techmap the constant
// source. Otherwise techmap the fabric source.
generate for (i = 0; i < 1; i = i + 1) begin:slice
CARRY0 #(.CYINIT_FABRIC(1)) carry(
.CI_INIT(CI),
.DI(AA[0]),
.S(S[0]),
.CO_CHAIN(CO_CHAIN[0]),
.CO_FABRIC(CO[0]),
.O(Y[0])
);
end endgenerate
generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
if(i % 4 == 0) begin
CARRY0 carry (
.CI(C[i]),
.DI(AA[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.CO_FABRIC(CO[i]),
.O(Y[i])
);
end
else
begin
CARRY carry (
.CI(C[i]),
.DI(AA[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.CO_FABRIC(CO[i]),
.O(Y[i])
);
end
end endgenerate
generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
if(i % 4 == 0) begin
CARRY0 top_of_carry (
.CI(C[i]),
.DI(AA[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.O(Y[i])
);
end
else
begin
CARRY top_of_carry (
.CI(C[i]),
.DI(AA[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.O(Y[i])
);
end
// Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
// a non-congested path to output the top of the carry chain.
// Registering the output of the CARRY block would solve this, but not
// all designs do that.
if((i+1) % 4 == 0) begin
CARRY0 carry_output (
.CI(CO_CHAIN[i]),
.DI(0),
.S(0),
.O(CO[i])
);
end
else
begin
CARRY carry_output (
.CI(CO_CHAIN[i]),
.DI(0),
.S(0),
.O(CO[i])
);
end
end endgenerate
end else begin end else begin
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;

23
techlibs/xilinx/cells_sim.v
View File

@ -455,29 +455,6 @@ module CARRY8(
assign CO[7] = S[7] ? CO[6] : DI[7]; assign CO[7] = S[7] ? CO[6] : DI[7];
endmodule endmodule
`ifdef _EXPLICIT_CARRY
module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
parameter CYINIT_FABRIC = 0;
wire CI_COMBINE;
if(CYINIT_FABRIC) begin
assign CI_COMBINE = CI_INIT;
end else begin
assign CI_COMBINE = CI;
end
assign CO_CHAIN = S ? CI_COMBINE : DI;
assign CO_FABRIC = S ? CI_COMBINE : DI;
assign O = S ^ CI_COMBINE;
endmodule
module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
assign CO_CHAIN = S ? CI : DI;
assign CO_FABRIC = S ? CI : DI;
assign O = S ^ CI;
endmodule
`endif
module ORCY (output O, input CI, I); module ORCY (output O, input CI, I);
assign O = CI | I; assign O = CI | I;
endmodule endmodule

15
techlibs/xilinx/synth_xilinx.cc
View File

@ -77,10 +77,6 @@ struct SynthXilinxPass : public ScriptPass
log(" write the design to the specified BLIF file. writing of an output file\n"); log(" write the design to the specified BLIF file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n"); log(" is omitted if this parameter is not specified.\n");
log("\n"); log("\n");
log(" -vpr\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -ise\n"); log(" -ise\n");
log(" generate an output netlist suitable for ISE\n"); log(" generate an output netlist suitable for ISE\n");
log("\n"); log("\n");
@ -142,7 +138,7 @@ struct SynthXilinxPass : public ScriptPass
} }
std::string top_opt, edif_file, blif_file, family; std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; bool flatten, retime, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
bool abc9, dff; bool abc9, dff;
bool flatten_before_abc; bool flatten_before_abc;
int widemux; int widemux;
@ -157,7 +153,6 @@ struct SynthXilinxPass : public ScriptPass
family = "xc7"; family = "xc7";
flatten = false; flatten = false;
retime = false; retime = false;
vpr = false;
ise = false; ise = false;
noiopad = false; noiopad = false;
noclkbuf = false; noclkbuf = false;
@ -229,10 +224,6 @@ struct SynthXilinxPass : public ScriptPass
nowidelut = true; nowidelut = true;
continue; continue;
} }
if (args[argidx] == "-vpr") {
vpr = true;
continue;
}
if (args[argidx] == "-ise") { if (args[argidx] == "-ise") {
ise = true; ise = true;
continue; continue;
@ -345,8 +336,6 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) { if (check_label("begin")) {
std::string read_args; std::string read_args;
if (vpr)
read_args += " -D_EXPLICIT_CARRY";
read_args += " -lib -specify +/xilinx/cells_sim.v"; read_args += " -lib -specify +/xilinx/cells_sim.v";
run("read_verilog" + read_args); run("read_verilog" + read_args);
@ -570,8 +559,6 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux); techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
if (!nocarry) { if (!nocarry) {
techmap_args += " -map +/xilinx/arith_map.v"; techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_args += " -D _EXPLICIT_CARRY";
} }
run("techmap " + techmap_args); run("techmap " + techmap_args);
run("opt -fast"); run("opt -fast");