mirror of https://github.com/YosysHQ/yosys.git
Fix omode which inserts an output if none exists (otherwise abc9 breaks)
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4d123b7638
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8182cb9d91
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@ -504,16 +504,16 @@ struct XAigerWriter
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aig_outputs.push_back(bit2aig(bit));
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}
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if (output_bits.empty()) {
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output_bits.insert(State::S0);
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omode = true;
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}
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for (auto bit : output_bits) {
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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}
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if (output_bits.empty()) {
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aig_o++;
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aig_outputs.push_back(0);
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omode = true;
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode)
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@ -575,6 +575,7 @@ struct XAigerWriter
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f << "c";
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log_assert(!output_bits.empty());
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auto write_buffer = [](std::stringstream &buffer, int i32) {
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int32_t i32_be = to_big_endian(i32);
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buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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@ -796,11 +797,11 @@ struct XAigerWriter
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f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
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output_lines.sort();
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if (omode)
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output_lines[State::S0] = "output 0 0 $__dummy__\n";
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for (auto &it : output_lines)
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f << it.second;
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log_assert(output_lines.size() == output_bits.size());
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if (omode && output_bits.empty())
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f << "output " << output_lines.size() << " 0 $__dummy__\n";
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wire_lines.sort();
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for (auto &it : wire_lines)
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