mirror of https://github.com/YosysHQ/yosys.git
simcells: Fix reset polarity for $_DLATCH_???_ cells.
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@ -300,7 +300,7 @@ module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == {E:0|1})
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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@ -2986,7 +2986,7 @@ module \$_DLATCH_NP0_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == 0)
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if (R == 1)
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Q <= 0;
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else if (E == 0)
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Q <= D;
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@ -3009,7 +3009,7 @@ module \$_DLATCH_NP1_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == 0)
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if (R == 1)
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Q <= 1;
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else if (E == 0)
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Q <= D;
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@ -3032,7 +3032,7 @@ module \$_DLATCH_PN0_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == 1)
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if (R == 0)
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Q <= 0;
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else if (E == 1)
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Q <= D;
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@ -3055,7 +3055,7 @@ module \$_DLATCH_PN1_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == 1)
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if (R == 0)
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Q <= 1;
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else if (E == 1)
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Q <= D;
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