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aigsize: Remove
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@ -1434,70 +1434,4 @@ struct XAiger2Backend : Backend {
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}
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} XAiger2Backend;
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struct AIGCounter : Index<AIGCounter, int> {
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typedef int Lit;
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const static Lit CONST_FALSE = -1;
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const static Lit CONST_TRUE = 1;
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const static constexpr Lit EMPTY_LIT = 0;
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static Lit negate(Lit lit) { return -lit; }
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int nvars = 1;
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int ngates = 0;
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Lit emit_gate([[maybe_unused]] Lit a, [[maybe_unused]] Lit b)
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{
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ngates++;
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return ++nvars;
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}
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void count() {
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// populate inputs
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for (auto w : top->wires())
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if (w->port_input)
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for (int i = 0; i < w->width; i++)
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pi_literal(SigBit(w, i)) = ++nvars;
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for (auto w : top->wires())
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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(void) eval_po(bit);
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}
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}
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};
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struct AigsizePass : Pass {
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AigsizePass() : Pass("aigsize", "estimate AIG size for design") {}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing AIGSIZE pass. (size design AIG)\n");
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size_t argidx;
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AIGCounter writer;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-strash")
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writer.strashing = true;
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else if (args[argidx] == "-flatten")
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writer.flatten = true;
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else
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break;
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}
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extra_args(args, argidx, design);
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Module *top = design->top_module();
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if (!top || !design->selected_whole_module(top))
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log_cmd_error("No top module selected\n");
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design->bufNormalize(true);
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writer.setup(top);
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writer.count();
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log("Counted %d gates\n", writer.ngates);
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// we are leaving the sacred land, un-bufnormalize
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// (if not, this will lead to bugs: the buf-normalized
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// flag must not be kept on past the code that can work
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// with it)
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design->bufNormalize(false);
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}
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} AigsizePass;
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PRIVATE_NAMESPACE_END
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