Merge branch 'master' into wandwor

.gitignore

@@ -4,6 +4,7 @@
 *.gch
 *.gcda
 *.gcno
+__pycache__
 /.cproject
 /.project
 /.settings
@@ -28,6 +29,8 @@
 /yosys-smtbmc-script.py
 /yosys-filterlib
 /yosys-filterlib.exe
+/kernel/*.pyh
+/kernel/python_wrappers.cc
 /kernel/version_*.cc
 /share
 /yosys-win32-mxebin-*

Makefile

@@ -21,12 +21,14 @@ ENABLE_PROTOBUF := 0
 
 # python wrappers
 ENABLE_PYOSYS := 0
+ifeq ($(ENABLE_PYOSYS),1)
 PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)"
 PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
 PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"")
 PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.)
-PYTHON_PREFIX := `$(PYTHON_EXECUTABLE)-config --prefix`
+PYTHON_PREFIX := $(shell $(PYTHON_EXECUTABLE)-config --prefix)
 PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages
+endif
 
 # other configuration flags
 ENABLE_GCOV := 0
@@ -90,6 +92,9 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup
 # homebrew search paths
 ifneq ($(shell which brew),)
 BREW_PREFIX := $(shell brew --prefix)/opt
+$(info $$BREW_PREFIX is [${BREW_PREFIX}])
+CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
+LDFLAGS += -L$(BREW_PREFIX)/boost/lib
 CXXFLAGS += -I$(BREW_PREFIX)/readline/include
 LDFLAGS += -L$(BREW_PREFIX)/readline/lib
 PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)
@@ -273,30 +278,51 @@ endif
 ifeq ($(ENABLE_PYOSYS),1)
 
 #Detect name of boost_python library. Some distros usbe boost_python-py<version>, other boost_python<version>, some only use the major version number, some a concatenation of major and minor version numbers
+ifeq ($(OS), Darwin)
+BOOST_PYTHON_LIB ?= $(shell \
+	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1;        then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))";       else \
+	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1;  then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
+	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1;           then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))";          else \
+	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1;     then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))";    else \
+                                                                                                                                                                                        echo ""; fi; fi; fi; fi;)
+else
 BOOST_PYTHON_LIB ?= $(shell \
 	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1;        then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))";       else \
 	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1;  then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
 	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1;           then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))";          else \
 	if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1;     then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))";    else \
                                                                                                                                                                                         echo ""; fi; fi; fi; fi;)
+endif
 
 ifeq ($(BOOST_PYTHON_LIB),)
 $(error BOOST_PYTHON_LIB could not be detected. Please define manualy)
 endif
 
+ifeq ($(OS), Darwin)
 ifeq ($(PYTHON_MAJOR_VERSION),3)
-LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
+LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
-CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON
+CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON
 else
-LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
+LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
-CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON
+CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON
+endif
+else
+ifeq ($(PYTHON_MAJOR_VERSION),3)
+LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
+CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON
+else
+LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
+CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON
+endif
 endif
 
+ifeq ($(ENABLE_PYOSYS),1)
 PY_WRAPPER_FILE = kernel/python_wrappers
 OBJS += $(PY_WRAPPER_FILE).o
 PY_GEN_SCRIPT= py_wrap_generator
 PY_WRAP_INCLUDES := $(shell python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()")
 endif
+endif
 
 ifeq ($(ENABLE_READLINE),1)
 CXXFLAGS += -DYOSYS_ENABLE_READLINE
@@ -541,7 +567,11 @@ yosys$(EXE): $(OBJS)
 	$(P) $(LD) -o yosys$(EXE) $(LDFLAGS) $(OBJS) $(LDLIBS)
 
 libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
+ifeq ($(OS), Darwin)
+	$(P) $(LD) -o libyosys.so -shared -Wl,-install_name,libyosys.so $(LDFLAGS) $^ $(LDLIBS)
+else
 	$(P) $(LD) -o libyosys.so -shared -Wl,-soname,libyosys.so $(LDFLAGS) $^ $(LDLIBS)
+endif
 
 %.o: %.cc
 	$(Q) mkdir -p $(dir $@)
@@ -551,9 +581,11 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
 	$(Q) mkdir -p $(dir $@)
 	$(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P -
 
+ifeq ($(ENABLE_PYOSYS),1)
 $(PY_WRAPPER_FILE).cc: misc/$(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES)
 	$(Q) mkdir -p $(dir $@)
 	$(P) python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).gen_wrappers(\"$(PY_WRAPPER_FILE).cc\")"
+endif
 
 %.o: %.cpp
 	$(Q) mkdir -p $(dir $@)

backends/blif/blif.cc

@@ -409,12 +409,26 @@ struct BlifDumper
 
 			f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
 			for (auto &conn : cell->connections())
-			for (int i = 0; i < conn.second.size(); i++) {
+			{
-				if (conn.second.size() == 1)
+				if (conn.second.size() == 1) {
-					f << stringf(" %s", cstr(conn.first));
+					f << stringf(" %s=%s", cstr(conn.first), cstr(conn.second[0]));
-				else
+					continue;
-					f << stringf(" %s[%d]", cstr(conn.first), i);
+				}
-				f << stringf("=%s", cstr(conn.second.extract(i, 1)));
+
+				Module *m = design->module(cell->type);
+				Wire *w = m ? m->wire(conn.first) : nullptr;
+
+				if (w == nullptr) {
+					for (int i = 0; i < GetSize(conn.second); i++)
+						f << stringf(" %s[%d]=%s", cstr(conn.first), i, cstr(conn.second[i]));
+				} else {
+					for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) {
+						SigBit sig(w, i);
+						f << stringf(" %s[%d]=%s", cstr(conn.first), sig.wire->upto ?
+								sig.wire->start_offset+sig.wire->width-sig.offset-1 :
+								sig.wire->start_offset+sig.offset, cstr(conn.second[i]));
+					}
+				}
 			}
 			f << stringf("\n");
 

backends/btor/btor.cc

@@ -129,7 +129,13 @@ struct BtorWorker
 
 	void export_cell(Cell *cell)
 	{
-		log_assert(cell_recursion_guard.count(cell) == 0);
+		if (cell_recursion_guard.count(cell)) {
+			string cell_list;
+			for (auto c : cell_recursion_guard)
+				cell_list += stringf("\n    %s", log_id(c));
+			log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
+		}
+
 		cell_recursion_guard.insert(cell);
 		btorf_push(log_id(cell));
 

frontends/ast/ast.cc

@@ -196,6 +196,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 	is_string = false;
 	is_wand = false;
 	is_wor = false;
+	is_unsized = false;
 	was_checked = false;
 	range_valid = false;
 	range_swapped = false;
@@ -724,7 +725,7 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
 }
 
 // create an AST node for a constant (using a bit vector as value)
-AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
+AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized)
 {
 	AstNode *node = new AstNode(AST_CONSTANT);
 	node->is_signed = is_signed;
@@ -738,9 +739,15 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
 	node->range_valid = true;
 	node->range_left = node->bits.size()-1;
 	node->range_right = 0;
+	node->is_unsized = is_unsized;
 	return node;
 }
 
+AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
+{
+	return mkconst_bits(v, is_signed, false);
+}
+
 // create an AST node for a constant (using a string in bit vector form as value)
 AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
 {
@@ -777,6 +784,14 @@ bool AstNode::bits_only_01() const
 	return true;
 }
 
+RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
+{
+	RTLIL::State extbit = bits.back();
+	while (width > int(bits.size()))
+		bits.push_back(extbit);
+	return RTLIL::Const(bits);
+}
+
 RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
 {
 	std::vector<RTLIL::State> bits = this->bits;

frontends/ast/ast.h

@@ -173,7 +173,7 @@ namespace AST
 		// node content - most of it is unused in most node types
 		std::string str;
 		std::vector<RTLIL::State> bits;
-		bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked;
+		bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized;
 		int port_id, range_left, range_right;
 		uint32_t integer;
 		double realvalue;
@@ -262,6 +262,7 @@ namespace AST
 
 		// helper functions for creating AST nodes for constants
 		static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
+		static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);
 		static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
 		static AstNode *mkconst_str(const std::vector<RTLIL::State> &v);
 		static AstNode *mkconst_str(const std::string &str);
@@ -269,6 +270,7 @@ namespace AST
 		// helper function for creating sign-extended const objects
 		RTLIL::Const bitsAsConst(int width, bool is_signed);
 		RTLIL::Const bitsAsConst(int width = -1);
+		RTLIL::Const bitsAsUnsizedConst(int width);
 		RTLIL::Const asAttrConst();
 		RTLIL::Const asParaConst();
 		uint64_t asInt(bool is_signed);

frontends/ast/genrtlil.cc

@@ -904,7 +904,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (!range_valid)
 				log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
 
-			log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
+			if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
+				log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
 
 			RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
 			wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -966,8 +967,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				detectSignWidth(width_hint, sign_hint);
 			is_signed = sign_hint;
 
-			if (type == AST_CONSTANT)
+			if (type == AST_CONSTANT) {
-				return RTLIL::SigSpec(bitsAsConst());
+				if (is_unsized) {
+					return RTLIL::SigSpec(bitsAsUnsizedConst(width_hint));
+				} else {
+					return RTLIL::SigSpec(bitsAsConst());
+				}
+			}
 
 			RTLIL::SigSpec sig = realAsConst(width_hint);
 			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));

frontends/verilog/const2ast.cc

@@ -71,7 +71,7 @@ static int my_ilog2(int x)
 }
 
 // parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
-static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type)
+static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
 {
 	// all digits in string (MSB at index 0)
 	std::vector<uint8_t> digits;
@@ -129,6 +129,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 		return;
 	}
 
+	if (is_unsized && (len > len_in_bits))
+		log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
+
 	for (len = len - 1; len >= 0; len--)
 		if (data[len] == RTLIL::S1)
 			break;
@@ -186,7 +189,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 	// Simple base-10 integer
 	if (*endptr == 0) {
 		std::vector<RTLIL::State> data;
-		my_strtobin(data, str, -1, 10, case_type);
+		my_strtobin(data, str, -1, 10, case_type, false);
 		if (data.back() == RTLIL::S1)
 			data.push_back(RTLIL::S0);
 		return AstNode::mkconst_bits(data, true);
@@ -201,6 +204,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 	{
 		std::vector<RTLIL::State> data;
 		bool is_signed = false;
+		bool is_unsized = false;
 		if (*(endptr+1) == 's') {
 			is_signed = true;
 			endptr++;
@@ -209,28 +213,34 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 		{
 		case 'b':
 		case 'B':
-			my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
+			my_strtobin(data, endptr+2, len_in_bits, 2, case_type, false);
 			break;
 		case 'o':
 		case 'O':
-			my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
+			my_strtobin(data, endptr+2, len_in_bits, 8, case_type, false);
 			break;
 		case 'd':
 		case 'D':
-			my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
+			my_strtobin(data, endptr+2, len_in_bits, 10, case_type, false);
 			break;
 		case 'h':
 		case 'H':
-			my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
+			my_strtobin(data, endptr+2, len_in_bits, 16, case_type, false);
 			break;
 		default:
-			return NULL;
+			char next_char = char(tolower(*(endptr+1)));
+			if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') {
+				my_strtobin(data, endptr+1, 1, 2, case_type, true);
+				is_unsized = true;
+			} else {
+				return NULL;
+			}
 		}
 		if (len_in_bits < 0) {
 			if (is_signed && data.back() == RTLIL::S1)
 				data.push_back(RTLIL::S0);
 		}
-		return AstNode::mkconst_bits(data, is_signed);
+		return AstNode::mkconst_bits(data, is_signed, is_unsized);
 	}
 
 	return NULL;

frontends/verilog/verilog_lexer.l

@@ -234,7 +234,7 @@ YOSYS_NAMESPACE_END
 	return TOK_CONSTVAL;
 }
 
-[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_CONSTVAL;
 }

kernel/log.cc

@@ -230,6 +230,9 @@ static void logv_warning_with_prefix(const char *prefix,
 	}
 	else
 	{
+		int bak_log_make_debug = log_make_debug;
+		log_make_debug = 0;
+
 		for (auto &re : log_werror_regexes)
 			if (std::regex_search(message, re))
 				log_error("%s",  message.c_str());
@@ -254,6 +257,7 @@ static void logv_warning_with_prefix(const char *prefix,
 		}
 
 		log_warnings_count++;
+		log_make_debug = bak_log_make_debug;
 	}
 }
 
@@ -285,6 +289,9 @@ static void logv_error_with_prefix(const char *prefix,
 #ifdef EMSCRIPTEN
 	auto backup_log_files = log_files;
 #endif
+	int bak_log_make_debug = log_make_debug;
+	log_make_debug = 0;
+	log_suppressed();
 
 	if (log_errfile != NULL)
 		log_files.push_back(log_errfile);
@@ -298,6 +305,8 @@ static void logv_error_with_prefix(const char *prefix,
 	log("%s%s", prefix, log_last_error.c_str());
 	log_flush();
 
+	log_make_debug = bak_log_make_debug;
+
 	if (log_error_atexit)
 		log_error_atexit();
 

passes/opt/opt_clean.cc

@@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 			wire->attributes.erase("\\init");
 
 		if (GetSize(wire) == 0) {
-			// delete zero-width wires
+			// delete zero-width wires, unless they are module ports
-			goto delete_this_wire;
+			if (wire->port_id == 0)
+				goto delete_this_wire;
 		} else
 		if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
 			// do not delete anything with "keep" or module ports or initialized wires

passes/opt/opt_rmdff.cc

@@ -260,8 +260,8 @@ delete_dlatch:
 
 bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 {
-	RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
+	RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e;
-	RTLIL::Const val_cp, val_rp, val_rv;
+	RTLIL::Const val_cp, val_rp, val_rv, val_ep;
 
 	if (dff->type == "$_FF_") {
 		sig_d = dff->getPort("\\D");
@@ -285,6 +285,16 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
+	else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" &&
+			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
+			(dff->type[8] == 'N' || dff->type[8] == 'P')) {
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\C");
+		sig_e = dff->getPort("\\E");
+		val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
+		val_ep = RTLIL::Const(dff->type[7] == 'P', 1);
+	}
 	else if (dff->type == "$ff") {
 		sig_d = dff->getPort("\\D");
 		sig_q = dff->getPort("\\Q");
@@ -295,6 +305,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		sig_c = dff->getPort("\\CLK");
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 	}
+	else if (dff->type == "$dffe") {
+		sig_e = dff->getPort("\\EN");
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\CLK");
+		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
+		val_ep = RTLIL::Const(dff->parameters["\\EN_POLARITY"].as_bool(), 1);
+	}
 	else if (dff->type == "$adff") {
 		sig_d = dff->getPort("\\D");
 		sig_q = dff->getPort("\\Q");
@@ -337,39 +355,60 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		}
 	}
 
+	// If clock is driven by a constant and (i) no reset signal
+	//                                      (ii) Q has no initial value
+	//                                      (iii) initial value is same as reset value
 	if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
+		// Q is permanently reset value or initial value
 		mod->connect(sig_q, val_rv);
 		goto delete_dff;
 	}
 
+	// If D is fully undefined and reset signal present and (i) Q has no initial value
+	//                                                     (ii) initial value is same as reset value
 	if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
+		// Q is permanently reset value
 		mod->connect(sig_q, val_rv);
 		goto delete_dff;
 	}
 
+	// If D is fully undefined and no reset signal and Q has an initial value
 	if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
+		// Q is permanently initial value
 		mod->connect(sig_q, val_init);
 		goto delete_dff;
 	}
 
+	// If D is fully constant and (i) no reset signal
+	//                            (ii) reset value is same as constant D
+	//                        and (a) has no initial value
+	//                            (b) initial value same as constant D
 	if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
+		// Q is permanently D
 		mod->connect(sig_q, sig_d);
 		goto delete_dff;
 	}
 
+	// If D input is same as Q output and (i) no reset signal
+	//                                    (ii) no initial signal
+	//                                    (iii) initial value is same as reset value
 	if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) {
+		// Q is permanently reset value or initial value
 		if (sig_r.size())
 			mod->connect(sig_q, val_rv);
-		if (has_init)
+		else if (has_init)
 			mod->connect(sig_q, val_init);
 		goto delete_dff;
 	}
 
+	// If reset signal is present, and is fully constant
 	if (!sig_r.empty() && sig_r.is_fully_const())
 	{
+		// If reset value is permanently active or if reset is undefined
 		if (sig_r == val_rp || sig_r.is_fully_undef()) {
+			// Q is permanently reset value
 			mod->connect(sig_q, val_rv);
 			goto delete_dff;
 		}
@@ -389,6 +428,30 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		dff->unsetPort("\\R");
 	}
 
+	// If enable signal is present, and is fully constant
+	if (!sig_e.empty() && sig_e.is_fully_const())
+	{
+		// If enable value is permanently inactive
+		if (sig_e != val_ep) {
+			// Q is permanently initial value
+			mod->connect(sig_q, val_init);
+			goto delete_dff;
+		}
+
+		log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
+
+		if (dff->type == "$dffe") {
+			dff->type = "$dff";
+			dff->unsetPort("\\EN");
+			dff->unsetParam("\\EN_POLARITY");
+			return true;
+		}
+
+		log_assert(dff->type.substr(0,7) == "$_DFFE_");
+		dff->type = stringf("$_DFF_%c_", + dff->type[7]);
+		dff->unsetPort("\\E");
+	}
+
 	return false;
 
 delete_dff:
@@ -489,7 +552,8 @@ struct OptRmdffPass : public Pass {
 				if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_",
 						"$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
 						"$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_",
-						"$ff", "$dff", "$adff"))
+						"$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_",
+						"$ff", "$dff", "$dffe", "$adff"))
 					dff_list.push_back(cell->name);
 
 				if (cell->type.in("$dlatch", "$_DLATCH_P_", "$_DLATCH_N_"))

techlibs/xilinx/drams.txt

@@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D
 endbram
 
 match $__XILINX_RAM64X1D
+  min bits 5
+  min wports 1
   make_outreg
   or_next_if_better
 endmatch
 
 match $__XILINX_RAM128X1D
+  min bits 9
+  min wports 1
   make_outreg
 endmatch
 

tests/various/opt_rmdff.v

@@ -0,0 +1,50 @@
+module opt_rmdff_test (input C, input D, input E, output [29:0] Q);
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
+(* init = "1'b1" *) wire Q1; assign Q[1] = Q1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
+(* init = "1'b0" *) wire Q4; assign Q[4] = Q4;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
+(* init = "1'b0" *) wire Q7; assign Q[7] = Q7;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant
+
+\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
+(* init = "1'b1" *) wire Q9; assign Q[9] = Q9;
+\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active
+\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
+\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
+(* init = "1'b0" *) wire Q12; assign Q[12] = Q12;
+\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active
+
+\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
+(* init = "1'b1" *) wire Q14; assign Q[14] = Q14;
+\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active
+\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
+\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
+(* init = "1'b0" *) wire Q17; assign Q[17] = Q17;
+\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active
+
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
+(* init = "1'b1" *) wire Q19; assign Q[19] = Q19;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
+(* init = "1'b0" *) wire Q21; assign Q[21] = Q21;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value
+//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
+//                                                                                                           // (TODO, Q starts with 1'bx and becomes 1'b0)
+(* init = "1'b0" *) wire Q23; assign Q[23] = Q23;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active
+(* init = "1'b1" *) wire Q24; assign Q[24] = Q24;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active
+(* init = "1'b1" *) wire Q25; assign Q[25] = Q25;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
+(* init = "1'b1" *) wire Q29; assign Q[29] = Q29;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value
+
+endmodule

tests/various/opt_rmdff.ys

@@ -0,0 +1,26 @@
+read_verilog -icells opt_rmdff.v
+prep
+design -stash gold
+read_verilog -icells opt_rmdff.v
+proc
+opt_rmdff
+
+select -assert-count 0 c:remove*
+select -assert-min 7 c:keep*
+select -assert-count 0  t:$dffe 7:$_DFFE_* %u c:noenable* %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_simple -undef
+equiv_status -assert
+
+design -load gold
+stat
+
+design -load gate
+stat