mirror of https://github.com/YosysHQ/yosys.git
write_xaiger back to working with whole modules only
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parent
0806b8e398
commit
81548d1ef9
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@ -545,14 +545,11 @@ struct XAigerWriter
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undriven_bits.erase(bit);
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undriven_bits.erase(bit);
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if (!undriven_bits.empty() && !holes_mode) {
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if (!undriven_bits.empty() && !holes_mode) {
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bool whole_module = module->design->selected_whole_module(module->name);
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undriven_bits.sort();
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undriven_bits.sort();
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for (auto bit : undriven_bits) {
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for (auto bit : undriven_bits) {
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if (whole_module)
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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input_bits.insert(bit);
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input_bits.insert(bit);
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}
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}
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if (whole_module)
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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}
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