From 8cb3655ecdf89102213a33c7474fb85f1ad0a033 Mon Sep 17 00:00:00 2001 From: "Gabriel L. Somlo" Date: Fri, 28 Jun 2019 14:54:58 -0400 Subject: [PATCH 1/9] Make abc9 pass aware of optional ABCEXTERNAL override Signed-off-by: Gabriel Somlo --- passes/techmap/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index c45571b01..56f05eca4 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -10,6 +10,7 @@ OBJS += passes/techmap/abc.o OBJS += passes/techmap/abc9.o ifneq ($(ABCEXTERNAL),) passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' +passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' endif endif From dd8d264bf5b4a3d8230caf5ec7160f971131b33c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 29 Jun 2019 19:37:04 -0700 Subject: [PATCH 2/9] install *_nowide.lut files --- techlibs/ecp5/Makefile.inc | 1 + techlibs/xilinx/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index eee3b418f..ff39ba4fe 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 1a652eb27..e9ea10e48 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,8 +30,10 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) + $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) From 0067dc44f3928833eede2b9bb40260be78e11a93 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 09:44:53 -0700 Subject: [PATCH 3/9] Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG --- CHANGELOG | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 15dd5d002..5535ce418 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,6 +3,17 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -26,11 +37,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "synth_xilinx -nocarry" - Added "synth_xilinx -nowidelut" - Added "synth_ecp5 -nowidelut" - - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - - Added "synth_xilinx -abc9" (experimental) - - Added "synth_ice40 -abc9" (experimental) - - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB From 9018f29d54cb33328546580e0c7f9ee12e8a4ae3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 09:46:56 -0700 Subject: [PATCH 4/9] Move CHANGELOG entry from yosys-0.8 to 0.9 --- CHANGELOG | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b54897d89..818225e56 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,13 +2,6 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.9 .. Yosys 0.9-dev --------------------------- - - * Various - - Added "script -select" - - Yosys 0.9 .. Yosys 0.9-dev -------------------------- @@ -18,6 +11,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "script -select" Yosys 0.8 .. Yosys 0.8-dev From 6282a67332e9ca0ffe68b7ae57e93b6248946d4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 11:59:10 -0700 Subject: [PATCH 5/9] Space --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 818225e56..4348b3d7a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,7 @@ List of major changes and improvements between releases ======================================================= + Yosys 0.9 .. Yosys 0.9-dev -------------------------- From 02ba85b13302f0d20f6b51cc7fdff2fb953421df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:17:26 -0700 Subject: [PATCH 6/9] script -select -> script -scriptwire --- CHANGELOG | 2 +- kernel/yosys.cc | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 4348b3d7a..ae7d28236 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -12,7 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - Added "script -select" + - Added "script -scriptwire Yosys 0.8 .. Yosys 0.8-dev diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d4948881..456ad48a0 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); - log(" script -select [selection]\n"); + log(" script -scriptwire [selection]\n"); log("\n"); log("This command executes the yosys commands in the specified file (default\n"); log("behaviour), or commands embedded in the constant text value connected to the\n"); @@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - bool select_mode = false; + bool scriptwire = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-select") { - select_mode = true; + if (args[argidx] == "-scriptwire") { + scriptwire = true; continue; } break; } - if (select_mode) { + if (scriptwire) { extra_args(args, argidx, design); for (auto mod : design->selected_modules()) From 90382a0f6d1ad7dfd14ced95051e5e76de89491c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:19:23 -0700 Subject: [PATCH 7/9] Update test too --- tests/various/script.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 9ccc727eb..4152145e8 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -13,8 +13,8 @@ read_verilog -formal < Date: Tue, 2 Jul 2019 08:20:37 -0700 Subject: [PATCH 8/9] Use Pass::call_on_module() as per @cliffordwolf comments --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 456ad48a0..f95c0127b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass { if (!c.second.is_fully_const()) log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); auto v = c.second.as_const(); - Pass::call(design, v.decode_string()); + Pass::call_on_module(design, mod, v.decode_string()); } } else if (args.size() < 2) From 81a717e9b767792f64535757f905a5061c627fbd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:22:31 -0700 Subject: [PATCH 9/9] Update test for Pass::call_on_module() --- tests/various/script.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 4152145e8..66b7b5caa 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -9,7 +9,7 @@ read_verilog -formal <