mirror of https://github.com/YosysHQ/yosys.git
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
This commit is contained in:
parent
2b9c75f8e3
commit
80d9d15f1c
|
@ -0,0 +1 @@
|
||||||
|
read_verilog -sv reg_wire_error.sv
|
Loading…
Reference in New Issue