riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9: log which module is being operated on

This commit is contained in:
Eddie Hung 2020-01-13 09:43:57 -08:00
parent 9f3cb981d7
commit 808b388e34
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/techmap/abc9.cc
View File

@ -276,9 +276,11 @@ struct Abc9Pass : public ScriptPass
run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n",
active_design->scratchpad_get_int("write_xaiger.num_ands"),
active_design->scratchpad_get_int("write_xaiger.num_wires"),
log_id(mod),
active_design->scratchpad_get_int("write_xaiger.num_inputs"),
num_outputs);
if (num_outputs) {

4
passes/techmap/abc9_exe.cc
View File

@ -168,10 +168,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
std::string wire_delay, std::string tempdir_name
)
{
//FIXME:
//log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
// module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
std::string abc9_script;
if (!lut_costs.empty())