riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Check if RHS is empty first

This commit is contained in:
Eddie Hung 2019-07-18 15:22:00 -07:00
parent e22a752242
commit 802470746c
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/pmgen/xilinx_dsp.pmg
View File

@ -11,6 +11,7 @@ match ffA
select ffA->type.in($dff, $dffe) select ffA->type.in($dff, $dffe)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffA, \CLK_POLARITY).as_bool() select param(ffA, \CLK_POLARITY).as_bool()
filter !port(dsp, \A).remove_const().empty()
filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set()) filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
optional optional
endmatch endmatch
@ -24,6 +25,7 @@ match ffB
select ffB->type.in($dff, $dffe) select ffB->type.in($dff, $dffe)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffB, \CLK_POLARITY).as_bool() select param(ffB, \CLK_POLARITY).as_bool()
filter !port(dsp, \B).remove_const().empty()
filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set()) filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
optional optional
endmatch endmatch