mirror of https://github.com/YosysHQ/yosys.git
Improved dffsr2dff pass
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parent
d69395ca08
commit
801c022457
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@ -23,7 +23,7 @@
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USING_YOSYS_NAMESPACE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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PRIVATE_NAMESPACE_BEGIN
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void dffsr2dff_worker(SigMap &sigmap, Module *module, Cell *cell)
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void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
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{
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{
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if (cell->type == "$dffsr")
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if (cell->type == "$dffsr")
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{
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{
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@ -131,6 +131,49 @@ void dffsr2dff_worker(SigMap &sigmap, Module *module, Cell *cell)
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}
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}
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}
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}
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void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
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{
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if (cell->type == "$adff")
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{
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bool rstpol = cell->getParam("\\ARST_POLARITY").as_bool();
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SigBit rstunused = rstpol ? State::S0 : State::S1;
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SigSpec rstsig = sigmap(cell->getPort("\\ARST"));
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if (rstsig != rstunused)
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return;
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log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell));
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cell->type = "$dff";
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cell->unsetPort("\\ARST");
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cell->unsetParam("\\ARST_VALUE");
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cell->unsetParam("\\ARST_POLARITY");
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return;
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}
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if (cell->type.in("$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_"))
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{
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char clkpol = cell->type.c_str()[6];
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char rstpol = cell->type.c_str()[7];
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SigBit rstbit = sigmap(cell->getPort("\\R"));
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SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1;
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if (rstbit != rstunused)
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return;
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IdString newtype = stringf("$_DFF_%c_", clkpol);
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log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype));
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cell->type = newtype;
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cell->unsetPort("\\R");
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return;
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}
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}
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struct Dffsr2dffPass : public Pass {
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struct Dffsr2dffPass : public Pass {
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Dffsr2dffPass() : Pass("dffsr2dff", "convert DFFSR cells to simpler FF cell types") { }
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Dffsr2dffPass() : Pass("dffsr2dff", "convert DFFSR cells to simpler FF cell types") { }
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virtual void help()
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virtual void help()
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@ -139,8 +182,8 @@ struct Dffsr2dffPass : public Pass {
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log("\n");
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log("\n");
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log(" dffsr2dff [options] [selection]\n");
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log(" dffsr2dff [options] [selection]\n");
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log("\n");
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log("\n");
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log("This pass converts DFFSR cells ($dffsr, $_DFFSR_???_) to simpler FF cell types\n");
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log("This pass converts DFFSR cells ($dffsr, $_DFFSR_???_) and ADFF cells ($adff,\n");
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log("when one or both of the set/reset inputs is unused.\n");
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log("$_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.\n");
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log("\n");
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log("\n");
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}
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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@ -159,8 +202,10 @@ struct Dffsr2dffPass : public Pass {
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for (auto module : design->selected_modules()) {
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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for (auto cell : module->selected_cells()) {
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dffsr2dff_worker(sigmap, module, cell);
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dffsr_worker(sigmap, module, cell);
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adff_worker(sigmap, module, cell);
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}
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}
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}
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}
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}
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} Dffsr2dffPass;
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} Dffsr2dffPass;
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