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write_verilog: correctly map RTLIL `sync init`.

This commit is contained in:
whitequark 2018-12-07 18:48:06 +00:00
parent 435776120a
commit 7fe770a441
1 changed files with 2 additions and 0 deletions
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2
backends/verilog/verilog_backend.cc
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@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
if (sync->type == RTLIL::STa) { if (sync->type == RTLIL::STa) {
f << stringf("%s" "always @* begin\n", indent.c_str()); f << stringf("%s" "always @* begin\n", indent.c_str());
} else if (sync->type == RTLIL::STi) {
f << stringf("%s" "initial begin\n", indent.c_str());
} else { } else {
f << stringf("%s" "always @(", indent.c_str()); f << stringf("%s" "always @(", indent.c_str());
if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1) if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)