mirror of https://github.com/YosysHQ/yosys.git
Fixed propagation of width hints for $signed() and $unsigned()
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@ -950,7 +950,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// just pass thru the signal. the parent will evaluated the is_signed property and inperpret the SigSpec accordingly
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case AST_TO_SIGNED:
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case AST_TO_UNSIGNED: {
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RTLIL::SigSpec sig = children[0]->genRTLIL();
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int sub_width_hint;
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bool sub_sign_hint;
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children[0]->detectSignWidth(sub_width_hint, sub_sign_hint);
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RTLIL::SigSpec sig = children[0]->genRTLIL(width_hint, sub_sign_hint);
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is_signed = sign_hint;
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return sig;
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}
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