mirror of https://github.com/YosysHQ/yosys.git
read_aiger: ignore constant inputs on LUTs
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cd8f55a911
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@ -414,6 +414,10 @@ void AigerReader::parse_xaiger()
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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nodeID = parse_xaiger_literal(f);
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log_debug2("\t%u\n", nodeID);
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log_debug2("\t%u\n", nodeID);
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if (nodeID < 2) {
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log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
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continue;
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}
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RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
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RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
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log_assert(wire);
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log_assert(wire);
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input_sig.append(wire);
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input_sig.append(wire);
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@ -421,10 +425,10 @@ void AigerReader::parse_xaiger()
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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ce.clear();
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << GetSize(input_sig));
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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for (int j = 0; j < GetSize(lut_mask); ++j) {
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int gray = j ^ (j >> 1);
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
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ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
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RTLIL::SigBit o(output_sig);
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RTLIL::SigBit o(output_sig);
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bool success YS_ATTRIBUTE(unused) = ce.eval(o);
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bool success YS_ATTRIBUTE(unused) = ce.eval(o);
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log_assert(success);
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log_assert(success);
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