riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect

This commit is contained in:
Clifford Wolf 2014-02-08 19:13:19 +01:00
parent 926fa61119
commit 7f52c18a22
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
passes/memory/memory_collect.cc
View File

@ -160,6 +160,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
sig_rd_clk_enable.optimize();
sig_rd_clk_polarity.optimize();
sig_rd_transparent.optimize();
assert(sig_rd_clk.width == rd_ports);
assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());