riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

ABC -> ABC9

This commit is contained in:
Eddie Hung 2019-02-20 17:36:57 -08:00
parent e5b8bb9faa
commit 7f26043caf
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/abc9.cc
View File

@ -532,7 +532,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
ifs.close(); ifs.close();
log_header(design, "Re-integrating ABC results.\n"); log_header(design, "Re-integrating ABC9 results.\n");
RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n"); log_error("ABC output file does not contain a module `netlist'.\n");