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Merge branch 'towoe-unpacked_arrays'

This commit is contained in:
Clifford Wolf 2019-06-20 12:06:58 +02:00
parent 3b1e5264d8 6a6dd5e057
commit 7f1461d64b
2 changed files with 23 additions and 1 deletions
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8
frontends/verilog/verilog_parser.y
View File

@ -1400,7 +1400,13 @@ wire_name:
node->children.push_back(rng);
}
node->type = AST_MEMORY;
node->children.push_back($2);
auto *rangeNode = $2;
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
// SV array size [n], rewrite as [n-1:0]
rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
rangeNode->children.push_back(AstNode::mkconst_int(0, false));
}
node->children.push_back(rangeNode);
}
if (current_function_or_task == NULL) {
if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {

16
tests/simple/arrays02.sv Normal file
View File

@ -0,0 +1,16 @@
module uut_arrays02(clock, we, addr, wr_data, rd_data);
input clock, we;
input [3:0] addr, wr_data;
output [3:0] rd_data;
reg [3:0] rd_data;
reg [3:0] memory [16];
always @(posedge clock) begin
if (we)
memory[addr] <= wr_data;
rd_data <= memory[addr];
end
endmodule