mirror of https://github.com/YosysHQ/yosys.git
kernel/mem: Commit new values of attributes in emit.
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c86a79bf0b
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7f12820b26
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@ -210,6 +210,7 @@ void Mem::emit() {
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mem->width = width;
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mem->width = width;
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mem->start_offset = start_offset;
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mem->start_offset = start_offset;
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mem->size = size;
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mem->size = size;
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mem->attributes = attributes;
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for (auto &port : rd_ports) {
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for (auto &port : rd_ports) {
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// TODO: remove
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// TODO: remove
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log_assert(port.arst == State::S0);
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log_assert(port.arst == State::S0);
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@ -217,6 +218,7 @@ void Mem::emit() {
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log_assert(port.init_value == Const(State::Sx, width << port.wide_log2));
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log_assert(port.init_value == Const(State::Sx, width << port.wide_log2));
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if (!port.cell)
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memrd));
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port.cell = module->addCell(NEW_ID, ID($memrd));
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port.cell->attributes = port.attributes;
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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@ -232,6 +234,7 @@ void Mem::emit() {
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for (auto &port : wr_ports) {
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for (auto &port : wr_ports) {
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if (!port.cell)
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memwr));
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port.cell = module->addCell(NEW_ID, ID($memwr));
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port.cell->attributes = port.attributes;
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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@ -247,6 +250,7 @@ void Mem::emit() {
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for (auto &init : inits) {
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for (auto &init : inits) {
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if (!init.cell)
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if (!init.cell)
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init.cell = module->addCell(NEW_ID, ID($meminit));
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init.cell = module->addCell(NEW_ID, ID($meminit));
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init.cell->attributes = init.attributes;
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init.cell->parameters[ID::MEMID] = memid.str();
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init.cell->parameters[ID::MEMID] = memid.str();
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init.cell->parameters[ID::ABITS] = GetSize(init.addr);
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init.cell->parameters[ID::ABITS] = GetSize(init.addr);
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init.cell->parameters[ID::WIDTH] = width;
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init.cell->parameters[ID::WIDTH] = width;
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