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Update examples/cmos/counter.ys to use "synth" command 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-30 14:17:36 +02:00
parent 7fecc3c199
commit 7f0548c16f
1 changed files with 5 additions and 5 deletions
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examples/cmos/counter.ys
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@ -1,11 +1,12 @@
read_verilog counter.v
read_verilog -lib cmos_cells.v
proc;; memory;; techmap;;
synth
dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib;;
abc -liberty cmos_cells.lib
opt_clean
stat -liberty cmos_cells.lib
# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
# dfflibmap -liberty osu025_stdcells.lib
@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;;
write_verilog synth.v
write_spice synth.sp