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Use proper operator

This commit is contained in:
Miodrag Milanovic 2022-05-27 10:23:34 +02:00
parent b0c71ed594
commit 7ee570a75e
1 changed files with 4 additions and 4 deletions
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8
backends/firrtl/firrtl.cc
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@ -729,12 +729,12 @@ struct FirrtlWorker
always_uint = true;
firrtl_width = max(a_width, b_width);
}
else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
primop = "eq";
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
primop = "neq";
always_uint = true;
firrtl_width = 1;
@ -759,7 +759,7 @@ struct FirrtlWorker
always_uint = true;
firrtl_width = 1;
}
else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
// FIRRTL will widen the result (y) by the amount of the shift.
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
@ -777,7 +777,7 @@ struct FirrtlWorker
firrtl_width = a_width + (1 << b_width) - 1;
}
}
else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?