opt_lut: leave intact LUTs with cascade feeding module outputs.

This commit is contained in:
whitequark 2018-12-07 17:13:52 +00:00
parent 9eb03d458d
commit 7ec740b7ad
3 changed files with 26 additions and 0 deletions

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@ -225,6 +225,12 @@ struct OptLutWorker
log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB)); log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
if (index.query_is_output(lutA->getPort("\\Y")))
{
log(" Not combining LUTs (cascade connection feeds module output).\n");
continue;
}
pool<SigBit> lutA_inputs; pool<SigBit> lutA_inputs;
pool<SigBit> lutB_inputs; pool<SigBit> lutB_inputs;
for (auto &bit : lutA_input) for (auto &bit : lutA_input)

18
tests/opt/opt_lut_port.il Normal file
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@ -0,0 +1,18 @@
module $1
wire width 4 input 2 \_0_
wire output 4 \_1_
wire input 3 \_2_
wire output 1 \o
cell $lut \_3_
parameter \LUT 16'0011000000000011
parameter \WIDTH 4
connect \A { \_0_ [3] \o 2'00 }
connect \Y \_1_
end
cell $lut \_4_
parameter \LUT 4'0001
parameter \WIDTH 4
connect \A { 3'000 \_2_ }
connect \Y \o
end
end

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@ -0,0 +1,2 @@
read_ilang opt_lut_port.il
select -assert-count 2 t:$lut