riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix lexing of integer literals, fixes #1364 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-09-12 09:43:19 +02:00
parent f72765090c
commit 7eb593829f
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/verilog/const2ast.cc
View File

@ -199,13 +199,13 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
if (str == endptr) if (str == endptr)
len_in_bits = -1; len_in_bits = -1;
// The "<bits>'s?[bodhBODH]<digits>" syntax // The "<bits>'[sS]?[bodhBODH]<digits>" syntax
if (*endptr == '\'') if (*endptr == '\'')
{ {
std::vector<RTLIL::State> data; std::vector<RTLIL::State> data;
bool is_signed = false; bool is_signed = false;
bool is_unsized = len_in_bits < 0; bool is_unsized = len_in_bits < 0;
if (*(endptr+1) == 's') { if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
is_signed = true; is_signed = true;
endptr++; endptr++;
} }

2
frontends/verilog/verilog_lexer.l
View File

@ -239,7 +239,7 @@ YOSYS_NAMESPACE_END
return TOK_CONSTVAL; return TOK_CONSTVAL;
} }
[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ { [0-9]*[ \t]*\'[sS]?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext); frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONSTVAL; return TOK_CONSTVAL;
} }