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clockgate: bail on constant signals

This commit is contained in:
Emil J. Tywoniak 2024-09-09 21:20:19 +02:00
parent dc039d8be4
commit 7e473299bd
2 changed files with 48 additions and 1 deletions
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3
passes/techmap/clockgate.cc
View File

@ -151,7 +151,8 @@ struct ClockgatePass : public Pass {
continue; continue;
FfData ff(&initvals, cell); FfData ff(&initvals, cell);
if (ff.has_ce) { // It would be odd to get constants, but we better handle it
if (ff.has_ce && ff.sig_clk.is_wire() && ff.sig_ce.is_wire()) {
ce_ffs.insert(cell); ce_ffs.insert(cell);
ClkNetInfo info = clk_info_from_ff(ff); ClkNetInfo info = clk_info_from_ff(ff);

46
tests/techmap/clockgate.ys
View File

@ -125,4 +125,50 @@ select -module dffe_01 -assert-count 0 t:\\pdk_icg
select -module dffe_10 -assert-count 0 t:\\pdk_icg select -module dffe_10 -assert-count 0 t:\\pdk_icg
select -module dffe_11 -assert-count 0 t:\\pdk_icg select -module dffe_11 -assert-count 0 t:\\pdk_icg
#------------------------------------------------------------------------------
design -reset
read_rtlil << EOT
module \bad1
wire input 1 \clk
wire input 3 \d1
wire input 2 \en
wire output 4 \q1
cell $dffe $auto$ff.cc:266:slice$27
parameter \CLK_POLARITY 1
parameter \EN_POLARITY 1
parameter \WIDTH 1
connect \CLK \clk
connect \D \d1
connect \EN 1'1
connect \Q \q1
end
end
module \bad2
wire input 1 \clk
wire input 3 \d1
wire input 2 \en
wire output 4 \q1
cell $dffe $auto$ff.cc:266:slice$27
parameter \CLK_POLARITY 1
parameter \EN_POLARITY 1
parameter \WIDTH 1
connect \CLK 1'1
connect \D \d1
connect \EN \en
connect \Q \q1
end
end
EOT
# Check we don't choke on constants
clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
select -module bad1 -assert-count 0 t:\\pdk_icg
select -module bad2 -assert-count 0 t:\\pdk_icg
#------------------------------------------------------------------------------
# TODO test -tie_lo # TODO test -tie_lo