riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix TODOs

This commit is contained in:
Eddie Hung 2019-10-04 12:43:56 -07:00
parent 983068103e
commit 7de9c33931
2 changed files with 0 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
passes/pmgen/xilinx_dsp.pmg
View File

@ -103,11 +103,6 @@ code sigA sigB sigC sigD sigM clock
} }
else else
sigM = P; sigM = P;
// TODO: Check if necessary
// This sigM could have no users if downstream $add
// is narrower than $mul result, for example
if (sigM.empty())
reject;
clock = port(dsp, \CLK, SigBit()); clock = port(dsp, \CLK, SigBit());
endcode endcode
@ -159,16 +154,6 @@ match preAdd
optional optional
endmatch endmatch
code sigA sigD
// TODO: Check if this is necessary?
if (preAdd) {
sigA = port(preAdd, \A);
sigD = port(preAdd, \B);
if (GetSize(sigA) < GetSize(sigD))
std::swap(sigA, sigD);
}
endcode
// (4) If pre-adder was present, find match 'A' input for A2REG // (4) If pre-adder was present, find match 'A' input for A2REG
// If pre-adder was not present, move ADREG to A2REG // If pre-adder was not present, move ADREG to A2REG
// Then match 'A' input for A1REG // Then match 'A' input for A1REG

5
passes/pmgen/xilinx_dsp_CREG.pmg
View File

@ -79,11 +79,6 @@ endcode
// (attached to at most two $mux cells that implement clock-enable or // (attached to at most two $mux cells that implement clock-enable or
// reset functionality, using a subpattern discussed below) // reset functionality, using a subpattern discussed below)
code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
// TODO: Any downside to allowing this?
// If this DSP implements an accumulator, do not attempt to match
if (sigC == sigP)
reject;
argQ = sigC; argQ = sigC;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {