mirror of https://github.com/YosysHQ/yosys.git
Do not double count cells in abc
This commit is contained in:
parent
7a912f22b2
commit
7dc15bdd2d
|
@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
else
|
||||||
cell_stats[RTLIL::unescape_id(c->type)]++;
|
cell_stats[RTLIL::unescape_id(c->type)]++;
|
||||||
|
|
||||||
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
|
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
|
||||||
RTLIL::SigSig conn;
|
RTLIL::SigSig conn;
|
||||||
|
|
Loading…
Reference in New Issue