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synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro

This commit is contained in:
Eddie Hung 2020-01-10 15:07:46 -08:00
parent 291530c59f
commit 7d94e18100
1 changed files with 11 additions and 4 deletions
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15
techlibs/xilinx/synth_xilinx.cc
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@ -26,13 +26,16 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
struct SynthXilinxPass : public ScriptPass struct SynthXilinxPass : public ScriptPass
{ {
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
void on_register() YS_OVERRIDE
{
RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
}
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -555,7 +558,11 @@ struct SynthXilinxPass : public ScriptPass
run("techmap " + techmap_args); run("techmap " + techmap_args);
run("read_verilog -icells -lib +/xilinx/abc9_model.v"); run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
if (active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
abc9_opts += " -nomfs"; abc9_opts += " -nomfs";
if (nowidelut) if (nowidelut)
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";