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verific: Disable module existence check during static elaboration

This commit is contained in:
Miodrag Milanovic 2024-12-06 15:59:09 +01:00
parent 2ca611b4f4
commit 7d4aff618f
1 changed files with 46 additions and 23 deletions
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69
frontends/verific/verific.cc
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@ -2688,11 +2688,51 @@ struct VerificExtNets
} }
}; };
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
static msg_type_t prev_1063;
#endif
#ifdef VERIFIC_VHDL_SUPPORT
static msg_type_t prev_1240 ;
static msg_type_t prev_1241 ;
#endif
void save_blackbox_msg_state()
{
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
prev_1063 = Message::GetMessageType("VERI-1063") ;
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
#endif
#ifdef VERIFIC_VHDL_SUPPORT
prev_1240 = Message::GetMessageType("VHDL-1240") ;
prev_1241 = Message::GetMessageType("VHDL-1241") ;
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
#endif
}
void restore_blackbox_msg_state()
{
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
Message::ClearMessageType("VERI-1063") ;
if (Message::GetMessageType("VERI-1063")!=prev_1063)
Message::SetMessageType("VERI-1063", prev_1063);
#endif
#ifdef VERIFIC_VHDL_SUPPORT
Message::ClearMessageType("VHDL-1240") ;
Message::ClearMessageType("VHDL-1241") ;
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
Message::SetMessageType("VHDL-1240", prev_1240);
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
Message::SetMessageType("VHDL-1241", prev_1241);
#endif
}
void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED) void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
{ {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
save_blackbox_msg_state();
VerificExtensions::ElaborateAndRewrite(work, parameters); VerificExtensions::ElaborateAndRewrite(work, parameters);
verific_error_msg.clear(); verific_error_msg.clear();
restore_blackbox_msg_state();
#endif #endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (!ppfile.empty()) if (!ppfile.empty())
@ -2823,8 +2863,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) { if (static_elaborate) {
save_blackbox_msg_state();
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters); VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
verific_error_msg.clear(); verific_error_msg.clear();
restore_blackbox_msg_state();
#endif #endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (!ppfile.empty()) if (!ppfile.empty())
@ -3290,10 +3332,8 @@ struct VerificPass : public Pass {
return filename; return filename;
} }
#ifdef VERIFIC_VHDL_SUPPORT
msg_type_t prev_1240 ;
msg_type_t prev_1241 ;
#ifdef VERIFIC_VHDL_SUPPORT
void add_units_to_map(Map &map, std::string work, bool flag_lib) void add_units_to_map(Map &map, std::string work, bool flag_lib)
{ {
MapIter mi ; MapIter mi ;
@ -3306,11 +3346,7 @@ struct VerificPass : public Pass {
map.Insert(unit,unit); map.Insert(unit,unit);
} }
} }
save_blackbox_msg_state();
prev_1240 = Message::GetMessageType("VHDL-1240") ;
prev_1241 = Message::GetMessageType("VHDL-1241") ;
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
} }
void set_units_to_blackbox(Map &map, std::string work, bool flag_lib) void set_units_to_blackbox(Map &map, std::string work, bool flag_lib)
@ -3325,17 +3361,10 @@ struct VerificPass : public Pass {
unit->SetCompileAsBlackbox(); unit->SetCompileAsBlackbox();
} }
} }
Message::ClearMessageType("VHDL-1240") ; restore_blackbox_msg_state();
Message::ClearMessageType("VHDL-1241") ;
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
Message::SetMessageType("VHDL-1240", prev_1240);
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
Message::SetMessageType("VHDL-1241", prev_1241);
} }
#endif #endif
msg_type_t prev_1063;
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
void add_modules_to_map(Map &map, std::string work, bool flag_lib) void add_modules_to_map(Map &map, std::string work, bool flag_lib)
{ {
@ -3349,9 +3378,7 @@ struct VerificPass : public Pass {
map.Insert(veri_module,veri_module); map.Insert(veri_module,veri_module);
} }
} }
save_blackbox_msg_state();
prev_1063 = Message::GetMessageType("VERI-1063") ;
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
} }
void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib) void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib)
@ -3366,9 +3393,6 @@ struct VerificPass : public Pass {
veri_module->SetCompileAsBlackbox(); veri_module->SetCompileAsBlackbox();
} }
} }
Message::ClearMessageType("VERI-1063") ;
if (Message::GetMessageType("VERI-1063")!=prev_1063)
Message::SetMessageType("VERI-1063", prev_1063);
} }
#endif #endif
@ -3424,7 +3448,6 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1); RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1); RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1); RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851 // Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);