mirror of https://github.com/YosysHQ/yosys.git
Fix digit-formatting calculation for small numbers.
Calling log10() on zero causes a non-sensical value to be calculated. On some compile options, I've observed yosys crashing with an illegal instruction (SIGILL). To make it safe, fix the calculation to do a range check; wrap it a decimal_digits() function, and use it where the previous ceil(log10(n)) call was used. As a side, it also improves readability. Signed-off-by: Henner Zeller <h.zeller@acm.org>
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1f88a3de74
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@ -55,6 +55,10 @@ inline int32_t from_big_endian(int32_t i32) {
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#define log_debug2(...) ;
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#define log_debug2(...) ;
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//#define log_debug2(...) log_debug(__VA_ARGS__)
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//#define log_debug2(...) log_debug(__VA_ARGS__)
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static int decimal_digits(unsigned n) {
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return n > 1 ? ceil(log10(n)) : 1;
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}
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struct ConstEvalAig
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struct ConstEvalAig
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{
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{
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RTLIL::Module *module;
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RTLIL::Module *module;
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@ -515,7 +519,7 @@ void AigerReader::parse_aiger_ascii()
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unsigned l1, l2, l3;
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unsigned l1, l2, l3;
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// Parse inputs
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// Parse inputs
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int digits = ceil(log10(I));
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int digits = decimal_digits(I);
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for (unsigned i = 1; i <= I; ++i, ++line_count) {
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for (unsigned i = 1; i <= I; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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@ -537,7 +541,7 @@ void AigerReader::parse_aiger_ascii()
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clk_wire->port_input = true;
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clk_wire->port_input = true;
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clk_wire->port_output = false;
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clk_wire->port_output = false;
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}
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}
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digits = ceil(log10(L));
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digits = decimal_digits(L);
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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if (!(f >> l1 >> l2))
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if (!(f >> l1 >> l2))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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@ -575,7 +579,7 @@ void AigerReader::parse_aiger_ascii()
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}
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}
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// Parse outputs
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// Parse outputs
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digits = ceil(log10(O));
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digits = decimal_digits(O);
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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@ -643,7 +647,7 @@ void AigerReader::parse_aiger_binary()
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std::string line;
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std::string line;
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// Parse inputs
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// Parse inputs
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int digits = ceil(log10(I));
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int digits = decimal_digits(I);
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for (unsigned i = 1; i <= I; ++i) {
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for (unsigned i = 1; i <= I; ++i) {
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log_debug2("%d is an input\n", i);
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log_debug2("%d is an input\n", i);
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RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
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RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
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@ -662,7 +666,7 @@ void AigerReader::parse_aiger_binary()
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clk_wire->port_input = true;
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clk_wire->port_input = true;
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clk_wire->port_output = false;
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clk_wire->port_output = false;
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}
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}
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digits = ceil(log10(L));
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digits = decimal_digits(L);
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l1 = (I+1) * 2;
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l1 = (I+1) * 2;
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for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
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for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
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if (!(f >> l2))
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if (!(f >> l2))
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@ -700,7 +704,7 @@ void AigerReader::parse_aiger_binary()
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}
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}
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// Parse outputs
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// Parse outputs
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digits = ceil(log10(O));
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digits = decimal_digits(O);
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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