mirror of https://github.com/YosysHQ/yosys.git
Trim init attributes when resizing FFs in "wreduce", fixes #887
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
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da42f10765
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@ -54,6 +54,7 @@ struct WreduceWorker
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std::set<SigBit> work_queue_bits;
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std::set<SigBit> work_queue_bits;
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pool<SigBit> keep_bits;
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pool<SigBit> keep_bits;
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dict<SigBit, State> init_bits;
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dict<SigBit, State> init_bits;
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pool<SigBit> remove_init_bits;
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WreduceWorker(WreduceConfig *config, Module *module) :
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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config(config), module(module), mi(module) { }
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@ -164,6 +165,7 @@ struct WreduceWorker
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{
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{
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
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module->connect(sig_q[i], State::S0);
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module->connect(sig_q[i], State::S0);
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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sig_d.remove(i);
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sig_q.remove(i);
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sig_q.remove(i);
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continue;
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continue;
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@ -171,6 +173,7 @@ struct WreduceWorker
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
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module->connect(sig_q[i], sig_q[i-1]);
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module->connect(sig_q[i], sig_q[i-1]);
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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sig_d.remove(i);
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sig_q.remove(i);
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sig_q.remove(i);
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continue;
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continue;
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@ -178,6 +181,7 @@ struct WreduceWorker
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auto info = mi.query(sig_q[i]);
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auto info = mi.query(sig_q[i]);
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if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
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if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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sig_d.remove(i);
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sig_q.remove(i);
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sig_q.remove(i);
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zero_ext = false;
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zero_ext = false;
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@ -387,13 +391,16 @@ struct WreduceWorker
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void run()
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void run()
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{
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{
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// create a copy as mi.sigmap will be updated as we process the module
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SigMap init_attr_sigmap = mi.sigmap;
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for (auto w : module->wires()) {
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for (auto w : module->wires()) {
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if (w->get_bool_attribute("\\keep"))
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if (w->get_bool_attribute("\\keep"))
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for (auto bit : mi.sigmap(w))
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for (auto bit : mi.sigmap(w))
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keep_bits.insert(bit);
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keep_bits.insert(bit);
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if (w->attributes.count("\\init")) {
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if (w->attributes.count("\\init")) {
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Const initval = w->attributes.at("\\init");
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Const initval = w->attributes.at("\\init");
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SigSpec initsig = mi.sigmap(w);
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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int width = std::min(GetSize(initval), GetSize(initsig));
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for (int i = 0; i < width; i++)
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for (int i = 0; i < width; i++)
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init_bits[initsig[i]] = initval[i];
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init_bits[initsig[i]] = initval[i];
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@ -446,6 +453,24 @@ struct WreduceWorker
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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module->swap_names(w, nw);
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module->swap_names(w, nw);
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}
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}
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if (!remove_init_bits.empty()) {
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for (auto w : module->wires()) {
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if (w->attributes.count("\\init")) {
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Const initval = w->attributes.at("\\init");
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Const new_initval(State::Sx, GetSize(w));
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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for (int i = 0; i < width; i++) {
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log_dump(initsig[i], remove_init_bits.count(initsig[i]));
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if (!remove_init_bits.count(initsig[i]))
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new_initval[i] = initval[i];
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}
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w->attributes.at("\\init") = new_initval;
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log_dump(w->name, initval, new_initval);
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}
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}
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}
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}
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}
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};
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};
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