riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Improve import of memories via Verific 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-15 18:20:37 +01:00
parent bf402a806a
commit 7cf9d88028
1 changed files with 23 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
frontends/verific/verific.cc
View File

@ -1044,23 +1044,30 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_READ_PORT) if (inst->Type() == OPER_READ_PORT)
{ {
RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name())); RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()));
if (memory->width != int(inst->OutputSize())) int numchunks = int(inst->OutputSize()) / memory->width;
log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); int chunksbits = ceil_log2(numchunks);
RTLIL::SigSpec addr = operatorInput1(inst); if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0)
RTLIL::SigSpec data = operatorOutput(inst); log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
RTLIL::Cell *cell = module->addCell(inst_name, "$memrd"); for (int i = 0; i < numchunks; i++)
cell->parameters["\\MEMID"] = memory->name.str(); {
cell->parameters["\\CLK_ENABLE"] = false; RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
cell->parameters["\\CLK_POLARITY"] = true; RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
cell->parameters["\\TRANSPARENT"] = false;
cell->parameters["\\ABITS"] = GetSize(addr); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
cell->parameters["\\WIDTH"] = GetSize(data); RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd");
cell->setPort("\\CLK", RTLIL::State::Sx); cell->parameters["\\MEMID"] = memory->name.str();
cell->setPort("\\EN", RTLIL::State::Sx); cell->parameters["\\CLK_ENABLE"] = false;
cell->setPort("\\ADDR", addr); cell->parameters["\\CLK_POLARITY"] = true;
cell->setPort("\\DATA", data); cell->parameters["\\TRANSPARENT"] = false;
cell->parameters["\\ABITS"] = GetSize(addr);
cell->parameters["\\WIDTH"] = GetSize(data);
cell->setPort("\\CLK", RTLIL::State::Sx);
cell->setPort("\\EN", RTLIL::State::Sx);
cell->setPort("\\ADDR", addr);
cell->setPort("\\DATA", data);
}
continue; continue;
} }
@ -1068,7 +1075,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
{ {
RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
if (memory->width != int(inst->Input2Size())) if (memory->width != int(inst->Input2Size()))
log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
RTLIL::SigSpec addr = operatorInput1(inst); RTLIL::SigSpec addr = operatorInput1(inst);
RTLIL::SigSpec data = operatorInput2(inst); RTLIL::SigSpec data = operatorInput2(inst);