riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.

This commit is contained in:
Andrew Zonenberg 2016-12-16 15:14:20 +08:00
parent bea6e2f11f
commit 7cdba8432c
1 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
techlibs/greenpak4/cells_sim.v
View File

@ -49,6 +49,10 @@ module GP_BANDGAP(output reg OK);
endmodule endmodule
module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
module GP_COUNT8(input CLK, input wire RST, output reg OUT); module GP_COUNT8(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING"; parameter RESET_MODE = "RISING";
@ -132,7 +136,8 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
endmodule endmodule
module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN); module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
//TODO finish implementing
endmodule endmodule
module GP_DCMPREF(output reg[7:0]OUT); module GP_DCMPREF(output reg[7:0]OUT);
@ -144,22 +149,22 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2
always @(*) begin always @(*) begin
case(SEL) case(SEL)
2'b00: begin 2'd00: begin
OUTA <= IN0; OUTA <= IN0;
OUTB <= IN3; OUTB <= IN3;
end end
2'b01: begin 2'd01: begin
OUTA <= IN1; OUTA <= IN1;
OUTB <= IN2; OUTB <= IN2;
end end
2'b02: begin 2'd02: begin
OUTA <= IN2; OUTA <= IN2;
OUTB <= IN1; OUTB <= IN1;
end end
2'b03: begin 2'd03: begin
OUTA <= IN3; OUTA <= IN3;
OUTB <= IN0; OUTB <= IN0;
end end