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Fix spacing

This commit is contained in:
Eddie Hung 2020-02-18 08:30:41 -08:00
parent aa969f8778
commit 7c3b4b80ea
2 changed files with 68 additions and 68 deletions
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100
kernel/timinginfo.h
View File

@ -36,7 +36,7 @@ struct ModuleTiming
struct TimingInfo
{
dict<RTLIL::IdString, ModuleTiming> data;
dict<RTLIL::IdString, ModuleTiming> data;
TimingInfo()
{
@ -53,52 +53,52 @@ struct TimingInfo
if (!module->get_blackbox_attribute())
continue;
setup_module(module);
}
}
}
const ModuleTiming& setup_module(RTLIL::Module *module)
{
auto r = data.insert(module->name);
log_assert(r.second);
auto &t = r.first->second;
auto r = data.insert(module->name);
log_assert(r.second);
auto &t = r.first->second;
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
auto src = cell->getPort(ID(SRC));
auto dst = cell->getPort(ID(DST));
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
if (cell->getParam(ID(FULL)).as_bool()) {
for (const auto &s : src)
for (const auto &d : dst) {
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
r.first->second = max;
}
}
else {
log_assert(GetSize(src) == GetSize(dst));
for (auto i = 0; i < GetSize(src); i++) {
const auto &s = src[i];
const auto &d = dst[i];
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
r.first->second = max;
}
}
}
else if (cell->type == ID($specify3)) {
if (cell->type == ID($specify2)) {
auto src = cell->getPort(ID(SRC));
auto dst = cell->getPort(ID(DST));
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
if (cell->getParam(ID(FULL)).as_bool()) {
for (const auto &s : src)
for (const auto &d : dst) {
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
r.first->second = max;
}
}
else {
log_assert(GetSize(src) == GetSize(dst));
for (auto i = 0; i < GetSize(src); i++) {
const auto &s = src[i];
const auto &d = dst[i];
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
r.first->second = max;
}
}
}
else if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID(SRC));
auto dst = cell->getPort(ID(DST));
for (const auto &c : src.chunks())
@ -117,9 +117,9 @@ struct TimingInfo
continue;
}
for (const auto &d : dst) {
auto &v = t.arrival[d];
auto &v = t.arrival[d];
v = std::max(v, max);
}
}
}
else if (cell->type == ID($specrule)) {
auto type = cell->getParam(ID(TYPE)).decode_string();
@ -141,19 +141,19 @@ struct TimingInfo
continue;
}
for (const auto &s : src) {
auto &v = t.required[s];
auto &v = t.required[s];
v = std::max(v, max);
}
}
}
}
return t;
return t;
}
decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
decltype(data)::const_iterator end() const { return data.end(); }
int count(RTLIL::IdString module_name) const { return data.count(module_name); }
const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
decltype(data)::const_iterator end() const { return data.end(); }
int count(RTLIL::IdString module_name) const { return data.count(module_name); }
const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
};
YOSYS_NAMESPACE_END

36
passes/techmap/abc9_ops.cc
View File

@ -266,8 +266,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
if (ys_debug(1))
toposort.analyze_loops = true;
@ -382,7 +382,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
void prep_delays(RTLIL::Design *design, bool dff_mode)
{
TimingInfo timing;
TimingInfo timing;
// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
@ -412,7 +412,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
flops.insert(inst_module);
continue; // do not add $__ABC9_DELAY boxes to flops
// as delays will be captured in the flop box
// as delays will be captured in the flop box
}
if (!timing.count(derived_type))
@ -463,7 +463,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
void prep_lut(RTLIL::Design *design, int maxlut)
{
TimingInfo timing;
TimingInfo timing;
std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
for (auto module : design->modules()) {
@ -482,7 +482,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
else if (o != d)
log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
specify.push_back(i.second);
}
}
if (maxlut && GetSize(specify) > maxlut)
continue;
@ -523,7 +523,7 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
void prep_box(RTLIL::Design *design, bool dff_mode)
{
TimingInfo timing;
TimingInfo timing;
std::stringstream ss;
int abc9_box_id = 1;
@ -581,21 +581,21 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
first = false;
else
ss << " ";
auto it = t.find(wire);
if (it == t.end())
auto it = t.find(wire);
if (it == t.end())
// Assume that no setup time means zero
ss << 0;
else {
ss << it->second;
ss << 0;
else {
ss << it->second;
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
log_id(port_name), it->second);
}
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
log_id(port_name), it->second);
}
#endif
}
}
}
// Last input is 'abc9_ff.Q'