mirror of https://github.com/YosysHQ/yosys.git
Fix spacing
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parent
aa969f8778
commit
7c3b4b80ea
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@ -36,7 +36,7 @@ struct ModuleTiming
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struct TimingInfo
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struct TimingInfo
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{
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{
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dict<RTLIL::IdString, ModuleTiming> data;
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dict<RTLIL::IdString, ModuleTiming> data;
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TimingInfo()
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TimingInfo()
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{
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{
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@ -53,52 +53,52 @@ struct TimingInfo
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if (!module->get_blackbox_attribute())
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if (!module->get_blackbox_attribute())
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continue;
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continue;
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setup_module(module);
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setup_module(module);
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}
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}
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}
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}
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const ModuleTiming& setup_module(RTLIL::Module *module)
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const ModuleTiming& setup_module(RTLIL::Module *module)
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{
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{
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auto r = data.insert(module->name);
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auto r = data.insert(module->name);
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log_assert(r.second);
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log_assert(r.second);
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auto &t = r.first->second;
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auto &t = r.first->second;
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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if (cell->type == ID($specify2)) {
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if (cell->type == ID($specify2)) {
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auto src = cell->getPort(ID(SRC));
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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if (!c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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int max = std::max(rise_max,fall_max);
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int max = std::max(rise_max,fall_max);
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if (max < 0)
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if (max < 0)
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log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
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log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
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if (cell->getParam(ID(FULL)).as_bool()) {
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if (cell->getParam(ID(FULL)).as_bool()) {
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for (const auto &s : src)
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for (const auto &s : src)
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for (const auto &d : dst) {
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for (const auto &d : dst) {
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auto r = t.comb.insert(BitBit(s,d));
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auto r = t.comb.insert(BitBit(s,d));
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if (!r.second)
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if (!r.second)
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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r.first->second = max;
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r.first->second = max;
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}
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}
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}
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}
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else {
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else {
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log_assert(GetSize(src) == GetSize(dst));
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log_assert(GetSize(src) == GetSize(dst));
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for (auto i = 0; i < GetSize(src); i++) {
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for (auto i = 0; i < GetSize(src); i++) {
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const auto &s = src[i];
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const auto &s = src[i];
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const auto &d = dst[i];
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const auto &d = dst[i];
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auto r = t.comb.insert(BitBit(s,d));
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auto r = t.comb.insert(BitBit(s,d));
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if (!r.second)
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if (!r.second)
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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r.first->second = max;
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r.first->second = max;
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}
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}
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}
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}
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}
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}
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else if (cell->type == ID($specify3)) {
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else if (cell->type == ID($specify3)) {
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auto src = cell->getPort(ID(SRC));
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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for (const auto &c : src.chunks())
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@ -117,9 +117,9 @@ struct TimingInfo
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continue;
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continue;
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}
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}
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for (const auto &d : dst) {
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for (const auto &d : dst) {
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auto &v = t.arrival[d];
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auto &v = t.arrival[d];
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v = std::max(v, max);
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v = std::max(v, max);
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}
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}
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}
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}
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else if (cell->type == ID($specrule)) {
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else if (cell->type == ID($specrule)) {
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auto type = cell->getParam(ID(TYPE)).decode_string();
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auto type = cell->getParam(ID(TYPE)).decode_string();
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@ -141,19 +141,19 @@ struct TimingInfo
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continue;
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continue;
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}
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}
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for (const auto &s : src) {
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for (const auto &s : src) {
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auto &v = t.required[s];
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auto &v = t.required[s];
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v = std::max(v, max);
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v = std::max(v, max);
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}
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}
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}
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}
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}
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}
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return t;
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return t;
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}
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}
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decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
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decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
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decltype(data)::const_iterator end() const { return data.end(); }
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decltype(data)::const_iterator end() const { return data.end(); }
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int count(RTLIL::IdString module_name) const { return data.count(module_name); }
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int count(RTLIL::IdString module_name) const { return data.count(module_name); }
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const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
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const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
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};
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};
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YOSYS_NAMESPACE_END
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YOSYS_NAMESPACE_END
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@ -266,8 +266,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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for (auto &it : bit_users)
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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toposort.edge(driver_cell, user_cell);
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if (ys_debug(1))
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if (ys_debug(1))
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toposort.analyze_loops = true;
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toposort.analyze_loops = true;
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@ -382,7 +382,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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void prep_delays(RTLIL::Design *design, bool dff_mode)
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void prep_delays(RTLIL::Design *design, bool dff_mode)
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{
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{
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TimingInfo timing;
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TimingInfo timing;
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// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
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// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
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// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
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// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
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@ -412,7 +412,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
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if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
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flops.insert(inst_module);
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flops.insert(inst_module);
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continue; // do not add $__ABC9_DELAY boxes to flops
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continue; // do not add $__ABC9_DELAY boxes to flops
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// as delays will be captured in the flop box
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// as delays will be captured in the flop box
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}
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}
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if (!timing.count(derived_type))
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if (!timing.count(derived_type))
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@ -463,7 +463,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
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void prep_lut(RTLIL::Design *design, int maxlut)
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void prep_lut(RTLIL::Design *design, int maxlut)
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{
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{
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TimingInfo timing;
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TimingInfo timing;
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std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
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std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
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for (auto module : design->modules()) {
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for (auto module : design->modules()) {
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@ -482,7 +482,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
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else if (o != d)
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else if (o != d)
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log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
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log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
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specify.push_back(i.second);
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specify.push_back(i.second);
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}
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}
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if (maxlut && GetSize(specify) > maxlut)
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if (maxlut && GetSize(specify) > maxlut)
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continue;
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continue;
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@ -523,7 +523,7 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
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void prep_box(RTLIL::Design *design, bool dff_mode)
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void prep_box(RTLIL::Design *design, bool dff_mode)
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{
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{
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TimingInfo timing;
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TimingInfo timing;
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std::stringstream ss;
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std::stringstream ss;
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int abc9_box_id = 1;
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int abc9_box_id = 1;
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@ -581,21 +581,21 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
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first = false;
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first = false;
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else
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else
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ss << " ";
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ss << " ";
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auto it = t.find(wire);
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auto it = t.find(wire);
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if (it == t.end())
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if (it == t.end())
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// Assume that no setup time means zero
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// Assume that no setup time means zero
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ss << 0;
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ss << 0;
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else {
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else {
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ss << it->second;
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ss << it->second;
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#ifndef NDEBUG
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#ifndef NDEBUG
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if (ys_debug(1)) {
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
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if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
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log_id(port_name), it->second);
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log_id(port_name), it->second);
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}
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}
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#endif
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#endif
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}
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}
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}
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}
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// Last input is 'abc9_ff.Q'
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// Last input is 'abc9_ff.Q'
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