mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1562 from whitequark/write_cxxrtl
write_cxxrtl: new backend
This commit is contained in:
commit
7c06cb6157
1
Makefile
1
Makefile
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@ -546,6 +546,7 @@ $(eval $(call add_include_file,libs/json11/json11.hpp))
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$(eval $(call add_include_file,passes/fsm/fsmdata.h))
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$(eval $(call add_include_file,passes/fsm/fsmdata.h))
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$(eval $(call add_include_file,frontends/ast/ast.h))
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$(eval $(call add_include_file,frontends/ast/ast.h))
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$(eval $(call add_include_file,backends/ilang/ilang_backend.h))
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$(eval $(call add_include_file,backends/ilang/ilang_backend.h))
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$(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h))
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OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
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OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
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OBJS += kernel/cellaigs.o kernel/celledges.o
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OBJS += kernel/cellaigs.o kernel/celledges.o
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@ -0,0 +1,2 @@
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OBJS += backends/cxxrtl/cxxrtl.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1034,6 +1034,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
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command = "verilog";
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command = "verilog";
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else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0)
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else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0)
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command = "ilang";
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command = "ilang";
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else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".cc") == 0)
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command = "cxxrtl";
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else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0)
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else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0)
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command = "aiger";
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command = "aiger";
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else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0)
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else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0)
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@ -207,6 +207,7 @@ namespace RTLIL {
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struct SigSpec;
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struct SigSpec;
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struct Wire;
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struct Wire;
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struct Cell;
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struct Cell;
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struct Memory;
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struct Module;
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struct Module;
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struct Design;
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struct Design;
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struct Monitor;
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struct Monitor;
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@ -229,6 +230,7 @@ using RTLIL::Design;
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namespace hashlib {
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namespace hashlib {
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template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
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@ -236,6 +238,7 @@ namespace hashlib {
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template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
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