mirror of https://github.com/YosysHQ/yosys.git
Improve iCE40 SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
dca65d83a0
commit
7bf4e4a185
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@ -1283,7 +1283,7 @@ module SB_MAC16 (
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// Regs B and D
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reg [15:0] rB, rD;
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always @(posedge clock, posedge IRSTTOP) begin
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always @(posedge clock, posedge IRSTBOT) begin
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if (IRSTBOT) begin
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rB <= 0;
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rD <= 0;
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@ -1298,10 +1298,10 @@ module SB_MAC16 (
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// Multiplier Stage
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wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
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wire [15:0] Ah, Al, Bh, Bl;
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assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
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assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
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assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
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assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
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assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
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assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
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assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
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assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
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assign p_Ah_Bh = Ah * Bh;
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assign p_Al_Bh = Al * Bh;
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assign p_Ah_Bl = Ah * Bl;
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@ -1336,17 +1336,10 @@ module SB_MAC16 (
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assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
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// Adder Stage
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reg [31:0] P;
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always @* begin
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P = iG[7:0];
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P = P + (iG[15:8] + iK[7:0]) << 8;
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P = P + (iK[15:8] + iJ[7:0]) << 16;
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P = P + (iJ[15:8] + iF[7:0]) << 24;
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end
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assign iL = P;
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assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
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// Reg H
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reg [15:0] rH;
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reg [31:0] rH;
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always @(posedge clock, posedge IRSTBOT) begin
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if (IRSTBOT) begin
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rH <= 0;
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@ -1359,7 +1352,7 @@ module SB_MAC16 (
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// Hi Output Stage
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wire [15:0] XW, Oh;
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reg [15:0] rQ;
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assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
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assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
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assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
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assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
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assign CO = ACCUMCO ^ ADDSUBTOP;
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@ -1379,7 +1372,7 @@ module SB_MAC16 (
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// Lo Output Stage
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wire [15:0] YZ, Ol;
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reg [15:0] rS;
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assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
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assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
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assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
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assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
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assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
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@ -1387,7 +1380,7 @@ module SB_MAC16 (
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if (ORSTBOT) begin
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rS <= 0;
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end else if (CE) begin
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if (!OHOLDTOP) rS <= iR;
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if (!OHOLDBOT) rS <= iR;
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end
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end
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assign iS = rS;
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@ -1,2 +1,6 @@
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test_ffs_[01][01][01][01][01]_*
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test_bram_[0-9]*
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/test_ffs_[01][01][01][01][01]_*
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/test_bram_[0-9]*
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/test_dsp_model
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/test_dsp_model.vcd
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/test_dsp_model_ref.v
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/test_dsp_model_uut.v
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@ -1,87 +0,0 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Tue Feb 19 13:33:31 2019
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[*]
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[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
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[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
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[dumpfile_size] 119605
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[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
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[timestart] 0
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[size] 1850 1362
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[pos] 1816 32
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*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 223
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[signals_width] 142
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[sst_expanded] 1
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[sst_vpaned_height] 420
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@28
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testbench.CLK
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testbench.CE
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@200
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-
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@28
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testbench.REF_ACCUMCO
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testbench.UUT_ACCUMCO
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@200
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-
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@28
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testbench.REF_CO
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testbench.UUT_CO
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@200
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-
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@22
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testbench.REF_O[31:0]
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testbench.UUT_O[31:0]
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@200
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-
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@28
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testbench.REF_SIGNEXTOUT
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testbench.UUT_SIGNEXTOUT
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@200
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-
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@22
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testbench.A[15:0]
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testbench.B[15:0]
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testbench.C[15:0]
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testbench.D[15:0]
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@200
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-
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@28
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testbench.AHOLD
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testbench.BHOLD
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testbench.CHOLD
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testbench.DHOLD
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@200
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-
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@28
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testbench.SIGNEXTIN
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testbench.ACCUMCI
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testbench.CI
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@200
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-
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@28
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testbench.ADDSUBTOP
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testbench.ADDSUBBOT
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@200
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-
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@28
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testbench.IRSTTOP
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testbench.IRSTBOT
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@200
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-
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@29
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testbench.OHOLDTOP
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@28
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testbench.OHOLDBOT
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@200
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-
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@28
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testbench.OLOADTOP
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testbench.OLOADBOT
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@200
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-
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@28
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testbench.ORSTTOP
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testbench.ORSTBOT
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[pattern_trace] 1
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[pattern_trace] 0
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@ -2,5 +2,10 @@
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set -ex
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sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
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iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
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./test_dsp_model
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for tb in testbench \
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testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
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testbench_seq_16x16_A testbench_seq_16x16_B
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do
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iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
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vvp -N ./test_dsp_model
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done
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@ -11,13 +11,13 @@ module testbench;
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parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
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parameter [1:0] TOPOUTPUT_SELECT = 0;
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parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
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parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
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parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
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parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
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parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
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parameter [1:0] BOTOUTPUT_SELECT = 0;
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parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
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parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
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parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
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parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
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parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
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parameter [0:0] MODE_8x8 = 0;
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parameter [0:0] A_SIGNED = 0;
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parameter [0:0] B_SIGNED = 0;
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@ -46,7 +46,7 @@ module testbench;
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CLK = ~CLK;
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#2;
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if (REF_O !== UUT_O) begin
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$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
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$display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
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errcount = errcount + 1;
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end
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if (REF_CO !== UUT_CO) begin
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@ -69,29 +69,47 @@ module testbench;
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$dumpfile("test_dsp_model.vcd");
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$dumpvars(0, testbench);
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#5;
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#2;
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CLK = NEG_TRIGGER;
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CE = 1;
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{C, A, B, D} = 0;
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{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
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{IRSTTOP, IRSTBOT} = 0;
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{ORSTTOP, ORSTBOT} = 0;
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{OLOADTOP, OLOADBOT} = 0;
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{ADDSUBTOP, ADDSUBBOT} = 0;
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{OHOLDTOP, OHOLDBOT} = 0;
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{CI, ACCUMCI, SIGNEXTIN} = 0;
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// C = 10;
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// A = 15;
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// B = 22;
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// D = 27;
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{IRSTTOP, IRSTBOT} = ~0;
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{ORSTTOP, ORSTBOT} = ~0;
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repeat (10) clkcycle;
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#3;
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{IRSTTOP, IRSTBOT} = 0;
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{ORSTTOP, ORSTBOT} = 0;
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repeat (300) begin
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clkcycle;
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A = $urandom;
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B = $urandom;
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C = $urandom;
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D = $urandom;
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{AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
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{OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
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{ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
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{OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
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{CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
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{IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
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{ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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@ -197,3 +215,128 @@ module testbench;
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.SIGNEXTOUT (UUT_SIGNEXTOUT)
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);
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endmodule
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module testbench_comb_8x8_A;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_8x8_B;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_16x16;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_seq_16x16_A;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (1),
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.A_REG (1),
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.B_REG (1),
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.D_REG (1),
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.TOP_8x8_MULT_REG (1),
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.BOT_8x8_MULT_REG (1),
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.PIPELINE_16x16_MULT_REG1 (1),
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.PIPELINE_16x16_MULT_REG2 (1),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_seq_16x16_B;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (1),
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.A_REG (1),
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.B_REG (1),
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.D_REG (1),
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.TOP_8x8_MULT_REG (1),
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.BOT_8x8_MULT_REG (1),
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.PIPELINE_16x16_MULT_REG1 (1),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (1), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (1), // 0=R, 1=S, 2=8x8, 3=16x16
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||||
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
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.A_SIGNED (0),
|
||||
.B_SIGNED (0)
|
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) testbench ();
|
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endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue