mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'xc7dsp' into ice40dsp
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commit
7bdb3996e2
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@ -200,7 +200,7 @@ module \$__mul_gen (A, B, Y);
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.B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
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.Y(partial[n-1])
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);
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assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
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assign Y = partial_sum[n-1];
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end
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else begin
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