mirror of https://github.com/YosysHQ/yosys.git
cleaning up for PR
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ce069830c5
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7b964bfb83
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@ -1304,10 +1304,6 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
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}
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}
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inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
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inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
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if(sig.size() != 1 || sig.chunks().size() != 1) {
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std::cout << "rtp " << sig.size() << std::endl;
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std::cout << "rtp " << sig.chunks().size() << std::endl;
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}
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log_assert(sig.size() == 1 && sig.chunks().size() == 1);
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log_assert(sig.size() == 1 && sig.chunks().size() == 1);
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*this = SigBit(sig.chunks().front());
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*this = SigBit(sig.chunks().front());
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}
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}
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@ -290,7 +290,7 @@ struct EquivMakeWorker
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init_bit2driven();
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init_bit2driven();
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pool<Cell*> visited_cells;
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pool<Cell*> visited_cells;
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for (auto c : cells_list)
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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for (auto &conn : c->connections())
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if (!ct.cell_output(c->type, conn.first)) {
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if (!ct.cell_output(c->type, conn.first)) {
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@ -418,7 +418,7 @@ struct EquivMakeWorker
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}
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}
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}
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}
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bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit)
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bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
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{
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{
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if (source_bit == target_bit)
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if (source_bit == target_bit)
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return true;
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return true;
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