diff --git a/passes/pmgen/peepopt_shiftmul_right.pmg b/passes/pmgen/peepopt_shiftmul_right.pmg
index 71e098023..108829d4f 100644
--- a/passes/pmgen/peepopt_shiftmul_right.pmg
+++ b/passes/pmgen/peepopt_shiftmul_right.pmg
@@ -82,22 +82,17 @@ code
 	int new_const_factor = 1 << factor_bits;
 	SigSpec padding(State::Sx, new_const_factor-const_factor);
 	SigSpec old_a = port(shift, \A), new_a;
-	int trunc = 0;
-
-	if (GetSize(old_a) % const_factor != 0) {
-		trunc = const_factor - GetSize(old_a) % const_factor;
-		old_a.append(SigSpec(State::Sx, trunc));
-	}
 
 	for (int i = 0; i*const_factor < GetSize(old_a); i++) {
-		SigSpec slice = old_a.extract(i*const_factor, const_factor);
-		new_a.append(slice);
-		new_a.append(padding);
+		if ((i+1)*const_factor < GetSize(old_a)) {
+			SigSpec slice = old_a.extract(i*const_factor, const_factor);
+			new_a.append(slice);
+			new_a.append(padding);
+		} else {
+			new_a.append(old_a.extract_end(i*const_factor));
+		}
 	}
 
-	if (trunc > 0)
-		new_a.remove(GetSize(new_a)-trunc, trunc);
-
 	SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
 	if (param(shift, \B_SIGNED).as_bool())
 		new_b.append(State::S0);
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 45e936a21..cbbd477e8 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -46,7 +46,31 @@ design -import gold -as gold peepopt_shiftmul_2
 design -import gate -as gate peepopt_shiftmul_2
 
 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
-sat -show-public -enable_undef -prove-asserts miter
+sat -verify -show-public -enable_undef -prove-asserts miter
+cd gate
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_3 (input [7:0] D, input [0:0] S, output [3:0] Y);
+	assign Y = D >> (S*5);
+endmodule
+EOT
+
+prep
+design -save gold
+peepopt
+design -stash gate
+
+design -import gold -as gold peepopt_shiftmul_3
+design -import gate -as gate peepopt_shiftmul_3
+
+miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
+sat -verify -show-public -enable_undef -prove-asserts miter
 cd gate
 select -assert-count 1 t:$shr
 select -assert-count 1 t:$mul