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Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-07-02 11:36:26 +02:00 committed by David Shah
parent fc87c010c5
commit 7b298479d4
1 changed files with 2 additions and 0 deletions
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frontends/verilog/verilog_lexer.l
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@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
global state.. its a mess) */ global state.. its a mess) */
[a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
if (!strcmp(yytext, "default"))
return TOK_DEFAULT;
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_SVA_LABEL; return TOK_SVA_LABEL;
} }